A Novel High Performance Low Power Universal Gate Implementation in Subthreshold Region
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10.5120/15261-3938 |
Ankish Handa, Paanshul Dobriyal and Geetanjali Sharma. Article: A Novel High Performance Low Power Universal Gate Implementation in Subthreshold Region. International Journal of Computer Applications 87(12):21-25, February 2014. Full text available. BibTeX
@article{key:article,
author = {Ankish Handa and Paanshul Dobriyal and Geetanjali Sharma},
title = {Article: A Novel High Performance Low Power Universal Gate Implementation in Subthreshold Region},
journal = {International Journal of Computer Applications},
year = {2014},
volume = {87},
number = {12},
pages = {21-25},
month = {February},
note = {Full text available}
}
Abstract
In any integrated circuit power consumption plays a paramount role and is considered as one of the top challenges in International technology roadmap for semiconductors. In this paper, a low power circuit designed to operate in subthreshold region is proposed. Voltage scaling technique is incorporated to reduce dynamic power consumption while static or leakage power is greatly reduced with forced stack technique. The present technique (VS-STACK) features very low power dissipation as compared to its standard CMOS counterparts in subthreshold region. The power consumption is curtailed by 20% to 90% together with a better power delay product (PDP) over a supply voltage range. The technique is tested on a 2-input NOR gate in the 45nm process. Tanner Tool EDA 13. 0v is used for simulation.
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