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Reseach Article

Design of Low Transition Pseudo-Random Pattern Generator for BIST Applications

by Lubna Naim, Tarana A. Chandel
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 87 - Number 15
Year of Publication: 2014
Authors: Lubna Naim, Tarana A. Chandel
10.5120/15285-3924

Lubna Naim, Tarana A. Chandel . Design of Low Transition Pseudo-Random Pattern Generator for BIST Applications. International Journal of Computer Applications. 87, 15 ( February 2014), 26-30. DOI=10.5120/15285-3924

@article{ 10.5120/15285-3924,
author = { Lubna Naim, Tarana A. Chandel },
title = { Design of Low Transition Pseudo-Random Pattern Generator for BIST Applications },
journal = { International Journal of Computer Applications },
issue_date = { February 2014 },
volume = { 87 },
number = { 15 },
month = { February },
year = { 2014 },
issn = { 0975-8887 },
pages = { 26-30 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume87/number15/15285-3924/ },
doi = { 10.5120/15285-3924 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:06:01.014905+05:30
%A Lubna Naim
%A Tarana A. Chandel
%T Design of Low Transition Pseudo-Random Pattern Generator for BIST Applications
%J International Journal of Computer Applications
%@ 0975-8887
%V 87
%N 15
%P 26-30
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Built in self testing (BIST) is most attractive technique to test different kind of circuits. In BIST, test patterns are generated by different techniques of test pattern generation and applied to the circuit under test (CUT). In pseudorandom BIST architecture, test patterns are generated by Linear Feedback Shift Register (LFSR). Due to high Switching in pattern generation by conventional LFSR, power dissipation is high in conventional LFSR. Power is an important constraint in VLSI (Very Large Scale Integration) testing. This paper presents a modification in LFSR to generate pattern for BIST applications with reduced power requirement. This new technique represent low transition pattern pseudorandom generator (LT-PRG) for Test-per-Clock and Test-per-Scan BIST applications. The LT-PRPG is designed with the use of a LFSR and a 2x1 multiplexer. Experimental results show that the implementation of Bit-Swapping LFSR can reduce the internal transition activity probability which directly affect the dissipation of power in CUT without affecting the fault coverage.

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Index Terms

Computer Science
Information Sciences

Keywords

Built-in-Self-Test(BIST) Bit-Swapping LFSR(BS-LFSR) Weighted Switching activity Test pattern generation Transition Low Power