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Reseach Article

Design and Comparative Analysis of SRAM Cell Structures using 0.5 mm Technology

by Prachi Jain, Sheetesh Sad, Janakrani Wadhawan
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 87 - Number 3
Year of Publication: 2014
Authors: Prachi Jain, Sheetesh Sad, Janakrani Wadhawan
10.5120/15190-3562

Prachi Jain, Sheetesh Sad, Janakrani Wadhawan . Design and Comparative Analysis of SRAM Cell Structures using 0.5 mm Technology. International Journal of Computer Applications. 87, 3 ( February 2014), 29-34. DOI=10.5120/15190-3562

@article{ 10.5120/15190-3562,
author = { Prachi Jain, Sheetesh Sad, Janakrani Wadhawan },
title = { Design and Comparative Analysis of SRAM Cell Structures using 0.5 mm Technology },
journal = { International Journal of Computer Applications },
issue_date = { February 2014 },
volume = { 87 },
number = { 3 },
month = { February },
year = { 2014 },
issn = { 0975-8887 },
pages = { 29-34 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume87/number3/15190-3562/ },
doi = { 10.5120/15190-3562 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:06:23.707403+05:30
%A Prachi Jain
%A Sheetesh Sad
%A Janakrani Wadhawan
%T Design and Comparative Analysis of SRAM Cell Structures using 0.5 mm Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 87
%N 3
%P 29-34
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In rapid development of digital designs, memory is the most important building block, as half of the silicon area is used to store data value and program instructions . The power consumption and speed of SRAMs are important issue that has lead to multiple designs with the purpose of minimizing the power consumption. Speed and power consumption is the key parameter in ADC resolution. In this paper, we design and analyze 4-bit flash ADC by using 0. 5 µm CMOS technology in Tanner Tool. In the proposed design, we are using TIQ comparator and mux based encoder for converting analog signal in to digital signal, and analog input range is between 0 to 1. 36V, with the supply voltage of 2. 5V. Here we work on low power consumption of comparator which can be achieved by varying W/L ratio of PMOS and NMOS of TIQ comparator. The tool used for simulation purpose is S-Edit, T-Spice, W-Edit by Tanner Tool using hp0. 5µm CMOS technology at supply voltage of 2. 5volts.

References
  1. Evelyn Grossar, Michele Stucchi, Karen Maex and Wim Dehaene "Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies" IEEE J. Solid State Circuits, vol. no. pp. 2577-2588,Nov. 2006.
  2. Jan M. Rabaey, Anantha chandrakasan, Borivoje Nikolic, "Digital integrated circuit A design perspective" second addition, Prentice Hall electronics and VLSI series. Berkley, Calistoga, ICSE 2008 Proc. 2008, Johor Bahru, Malaysia Cambridge. 2003.
  3. Stefan Cosemans, Wim Dehaene and Francky Catthoor "A Low Power Embedded SRAM for Wireless Applications "IEEE J. Solid State Circuits, vol. 42, no. 7,pp. 1607-1610 July 2007.
  4. K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake, "A Readstatic-noise-margin-free SRAM cell for low-VDD and high-speed applications," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 113-121, Jan. 2006.
  5. Byung-Do Yang and Lee-Sup Kim "A Low Power SRAM using Hierrchical Bit Line and Local Sense Amplifiers" IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1366-1376, June 2005.
  6. Kouichi Kanda, Hattori Sadaaki, and Takayasu Sakurai "90% Write Power Saving SRAM Using Sense Amplifying Memory Cell" IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 927-933, June 2004.
  7. Shigeki Ohbayashi, Makoto Yabuuchi, Koji Niiand, Rajasekhar Keerthi and Chein-in Henry Chen "Stability and Static Noise Margin Analysis of Low-Power SRAM" I2MTC 2008 – IEEE International Instrumentation and Measurement Technology Conference, Victoria, Vancouver Island, Canada, May 12-15, 2008.
  8. Sung-Mo Kang, Yusuf Leblebici. "CMOS DIGITAL INTEGRATED CIRCUITS"; Analysis and Design, McGraw-Hill International Editions, Boston, 2nd Edition, 1999.
  9. Li-jun Zhang, Chen Wu, ya –oi ma jian bin,ling-feng "Leakage Power Reduction Techniques of 55nm SRAM Cells" IETE Technical Review Vol 28 Issue Mar-Apr 2011.
  10. Do Anh-Tuan, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan, and Kiat-Seng Yeo,"An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS" IEEE Transnctions on circuits and systems—I :regular papers, Vol. 58, No. 6, june 2011.
  11. S. Okumura et al. , "A 0. 56-V 128 kb 10T SRAM using column line assist (CLA) scheme," in Proc. ISQED, 2009, pp. 659–663.
  12. Qiaoyan Yu and Paul Ampadu "Cell Ratio Bounds for Reliable SRAM Operation", IEEE, pp: 1192-1195, 2006.
  13. Paridhi Athe and S. Dasgupta "A Comparative Study of 6T, 8T and 9T Deca nano SRAM cell", ISIEA, pp: 889-894, 2009.
  14. S. Lakshminarayan, J. Joung, G. Narasimhan, R. Kaper, M. Slanina, J. Tung, M. Whately "Standby Power Reduction and SRAM Cell optimization for 65nm Technology" 10th Int'l Symposium on Quality Electronic Design 2009 IEEE.
  15. Manpreet Kaur, Ravi Kumar Sharma,"Comparative Parametric Analysis For Stability Of 6t And 8t Sram Cell" International Journal of Advances In Engineering & Technology, Nov. 2012. ISSN: 2231-1963.
  16. Erik Brockmeyer, Lode Nachtergaele, Francky V. M. Catthoor, Jan Bormans, Hugo 1. De Man "Low Power Memory Storage and Transfer organization for the MPEG-4 Full Pel Motion Estimation on a Multimedia Processor" IEEE Transactions on Multimedia, vol. no. 21, pp. 202-216, June 1999.
  17. Kenneth W. Mai, Toshihiko Mori, Bharadwaj S. Amrutur, Ron Ho, Bennett Wilburn, Mark A. Horowotz, Isao Fukushi, Tetsuo Izawa, and Shin Mitarai "Low-Power SRAM Design Using HalfSwing Pulse-Mode Techniques" IEEE J. Solid-State Circuits, vol. 33, no. II,pp. 1659-1669, Nov. 1998.
  18. Tegze P. Haraszti "CMOS Memory Circuits" Kluwer Academic Publishers New York Boston, Dord Recht, London, Moscow,. 2002. pp. 61-132, 277-359.
  19. Stefan Cosemans, Wim Dehaene and Francky Catthoor "A Low Power Embedded SRAM for Wireless Applications "IEEE J. Solid State Circuits, vol. 42, no. 7,pp. 1607-1610 July 2007.
  20. E. Seevinck, F. J. List, and J. Lohstroh, "Static noise margin analysis ofMOS SRAM cells," IEEE J. Solid-State Circuits, vol. SC-22, no. 5,pp. 748-754,Oct. 1987. 121.
  21. Andrei Pavlov Manoj Sachdev, CMOS SRAM Circuit Design and parametric test in nano-scaled technologies Sedra & smith, Microelectronic circuits, oxford university press, fifth edition, 2004.
  22. Jan M Rabaey & Anantha Chandrakasan & Borivoje Nikolic, Digital integrated circuits-a design perspective, Pearson education, third edition,2005.
Index Terms

Computer Science
Information Sciences

Keywords

SRAM cell 6T SRAM cell 8T SRAM Cell 10 SRAM Cell and SNM