CFP last date
20 May 2024
Reseach Article

A Variable Threshold Voltage CMOS Comparator for Flash Analog to Digital Converter

by Gulrej Ahmed, Rajendra Kumar Baghel
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 88 - Number 7
Year of Publication: 2014
Authors: Gulrej Ahmed, Rajendra Kumar Baghel
10.5120/15367-3874

Gulrej Ahmed, Rajendra Kumar Baghel . A Variable Threshold Voltage CMOS Comparator for Flash Analog to Digital Converter. International Journal of Computer Applications. 88, 7 ( February 2014), 40-43. DOI=10.5120/15367-3874

@article{ 10.5120/15367-3874,
author = { Gulrej Ahmed, Rajendra Kumar Baghel },
title = { A Variable Threshold Voltage CMOS Comparator for Flash Analog to Digital Converter },
journal = { International Journal of Computer Applications },
issue_date = { February 2014 },
volume = { 88 },
number = { 7 },
month = { February },
year = { 2014 },
issn = { 0975-8887 },
pages = { 40-43 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume88/number7/15367-3874/ },
doi = { 10.5120/15367-3874 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:07:02.422301+05:30
%A Gulrej Ahmed
%A Rajendra Kumar Baghel
%T A Variable Threshold Voltage CMOS Comparator for Flash Analog to Digital Converter
%J International Journal of Computer Applications
%@ 0975-8887
%V 88
%N 7
%P 40-43
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents a variable threshold voltage CMOS comparator for flash analog to digital converter. The proposed comparator has single-ended type of architecture. The comparator is designed and analyzed by Cadence Virtuoso Analog Design Environment using UMC 180nm technology. The proposed comparator consumes peak power of 34. 97 ?W from 1. 8 V power supply. It achieves the power delay product (PDP) of 8 fJ and propagation delay of 230 ps. The designed comparator eliminates the requirement of resistive ladder network for reference voltage generation. This makes it highly suitable in the design of flash analog to digital converter.

References
  1. Goll, B. , & Zimmermann, H. 2009. A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0. 65 V, IEEE Transactions on Circuits and Systems II, 56(11), pp. 810-814.
  2. Ahmed, G. & Baghel, R. K. 2010. Design of High Performance CMOS Comparator with Low Power Consumption in 65nm Technology. International Journal of Electrical and Electronics, 3(1), pp. 199-204.
  3. Wulff, C. & Ytterdal, C. 2005. 0. 8V 1GHz dynamic comparator in digital 90nm CMOS technology, 23rd IEEE. NORCHIP Conference, pp. 237-240.
  4. Segura, J. , Rossello, J. L. , Morra, J. , & Sigg, H. 1998. A variable threshold voltage inverter for CMOS programmable logic circuits, IEEE Journal of Solid-State Circuits, 33(8), pp. 1262-1265.
  5. Tangel, A. , & Choi, K. 2004. The CMOS Inverter as a comparator in ADC designs. Analog Integrated Circuits and Signal Processing, 39(2), pp. 147-155.
  6. Rabaey, J. M. , Chandrakasan, A. and Nikolic?, B. 2006. Digital Integrated Circuits, PHI, 2nd Edition.
  7. Park, S. , & Flynn, M. P. 2006. A regenerative comparator structure with integrated inductors, IEEE Transactions on Circuits and Systems I, 53(8), pp. 1704-1711.
  8. Chandrakasan, A. P. , Sheng, S. & Brodersen, R. W. 1992. Low-power CMOS digital design, IEICE Transactions on Electronics, 75(4), pp. 371-382.
  9. Choi, M. , & Abidi, A. A. 2001. A 6-b 1. 3-Gsample/s A/D converter in 0. 35-?m CMOS. IEEE Journal of Solid-State Circuits, 36(12), pp. 1847-1858.
  10. Nikoozadeh, A. & Murmann, B. 2006. An analysis of latch comparator offset due to load capacitor mismatch, IEEE Transactions on Circuits and Systems II, 53(12), pp. 1398-1402.
  11. Solis, C. J. & Ducoudray, G. O. 2010. High resolution low power 0. 6 µm CMOS 40MHz dynamic latch comparator, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1045-1048.
  12. Miyahara, M. , Asada, Y. , Paik, D. & Matsuzawa, A. 2008. A low-noise self-calibrating dynamic comparator for high-speed ADCs, IEEE Asian Solid-State Circuits Conference, pp. 269-272.
  13. Razavi, B. & Wooley, B. A. 1992. Design techniques for high-speed, high-resolution comparators. IEEE Journal of Solid-State Circuits, 27(12), pp. 1916-1926.
  14. Jeon, H. & Kim, Y. B. 2010. A CMOS low-power low-offset and high-speed fully dynamic latched comparator. IEEE International SOC Conference (SOCC), pp. 285-288.
  15. Sadeghipour, K. D. 2011. Resolution enhanced latch comparator. 19th IEEE Iranian Conference on Electrical Engineering (ICEE), pp. 1-5.
  16. Sheikhaei, S. , Mirabbasi, S. & Ivanov, A. 2005. A 0. 35 ?m CMOS comparator circuit for high-speed ADC applications. IEEE International Symposium on Circuits and Systems, pp. 6134-6137.
  17. Steyaert, M. & Comino, V. 1988. High-speed accurate CMOS comparator, Electronics Letters, 24(16), pp. 1027-1028.
  18. Van der Plas, G. , Decoutere, S. & Donnay, S. 2006. A 0. 16 pJ/conversion-step 2. 5 mW 1. 25 GS/s 4b ADC in a 90nm digital CMOS process. IEEE International Solid-State Circuits, Digest of Technical Papers, p. 2310.
Index Terms

Computer Science
Information Sciences

Keywords

Variable threshold voltage threshold inverter quantization flash ADC power delay product.