Notification: Our email services are now fully restored after a brief, temporary outage caused by a denial-of-service (DoS) attack. If you sent an email on Dec 6 and haven't received a response, please resend your email.
CFP last date
20 December 2024
Reseach Article

Modified CPL Adiabatic Gated Logic – MCPLAG based DPET DFF with XOR

by Manoj Sharma, Arti Noor
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 89 - Number 19
Year of Publication: 2014
Authors: Manoj Sharma, Arti Noor
10.5120/15743-4701

Manoj Sharma, Arti Noor . Modified CPL Adiabatic Gated Logic – MCPLAG based DPET DFF with XOR. International Journal of Computer Applications. 89, 19 ( March 2014), 35-41. DOI=10.5120/15743-4701

@article{ 10.5120/15743-4701,
author = { Manoj Sharma, Arti Noor },
title = { Modified CPL Adiabatic Gated Logic – MCPLAG based DPET DFF with XOR },
journal = { International Journal of Computer Applications },
issue_date = { March 2014 },
volume = { 89 },
number = { 19 },
month = { March },
year = { 2014 },
issn = { 0975-8887 },
pages = { 35-41 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume89/number19/15743-4701/ },
doi = { 10.5120/15743-4701 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:09:43.305594+05:30
%A Manoj Sharma
%A Arti Noor
%T Modified CPL Adiabatic Gated Logic – MCPLAG based DPET DFF with XOR
%J International Journal of Computer Applications
%@ 0975-8887
%V 89
%N 19
%P 35-41
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The use of Adiabatic Logic in VLSI chip design has certainly promised positive aspects in terms of optimizing the power equations. In the reported work authors have extended their proposed CPLAG based 'XOR' implementation. The modified 'XOR' implementation is further configured to implement a dynamic positive edge triggered D flip flop. Both the reported circuits are functionally verified and found to be satisfactory to a high degree of signal integrity and accuracy. DFF circuit is further examined with different load, temperature range, transistor size and voltage levels. The results obtained from the proposed implementation of hybrid 'XOR' and DFF have showed good results. The average power at 1. 5V, 180nm, 25oC, 1fF load is 0. 209nW and 23-39nW for 0. 8v, 40oC for different run with Pclk_Q delay 0. 2ns, input_Q delay 16µs, Qtrise 44. 6µs, Qtfall 61µs, Qbtrise 4. 54µs, Qbtfall 3µs with 50. 9 zepto units PDP. The average power consumption for a conventional semi-adiabatic PFAL DFF is 35mW approx as compared to 0. 1µW for the implemented DFF.

References
  1. Manoj Sharma, Arti Noor. 2013. CPL-Adiabatic Gated logic (CPLAG) XOR gate. Advances in Computing, Communications and Informatics (ICACCI), 2013 International Conference on, (22-25 Aug. 2013), 575 – 579.
  2. Manoj Sharma, Arti Noor. 2013. Positive Feed Back Adiabatic Logic: PFAL Single Edge Triggered Semi-Adiabatic D Flip Flop. AJBAS, IDOSI (2013), 42-46.
  3. V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes. 2003. Synthesis of reversible logic circuits. IEEE Transactions on CAD, (June 2003), 22(6):723-729
  4. R. Landauer. 1961. Irreversibility and heat generation in the computing process. IBM Journal of Research and Development, (1961), vol. 5, 183- 191.
  5. C. H. Bennett. 1973. Logical reversibility of computation. IBM J. Res. Develop. (1973), vol. 17, no. 6, 525-532.
  6. Michael P. Frank. 2003. Common Mistakes in Adiabatic Logic Design and How to Avoid Them. International Conference on Embedded Systems and Applications, ESA '03. (June 23 - 26, 2003), 216-222, Las Vegas, Nevada, USA
  7. Michael P. Frank. 2002. Realistic Cost-Efficiency Advantages for Reversible Computing in Coming Decades. UF Reversible Computing Project Memo #M16, (Oct. 2002), http://www. cise. ufl. edu/-research/ revcomp/memos/ Memo16-three-d. doc.
  8. Prasad D Khandekar, Shaila Subbaraman, and Abhijit V. Chitre. 2010. Implementation and Analysis of Quasi-Adiabatic Inverters. Proceedings of the International MultiConference of Engineers and Computer Scientists (2010 March), Vol II, IMECS, 17-19, Hong Kong.
  9. Antonio Blotti and Roberto Saletti. 2004. Ultralow-Power Adiabatic Circuit Semi-Custom Design. IEEE transaction on Very Large Scale Integration (VLSI) systems. (2004 November), vol. 12, no. 11, 1248-1253.
  10. Kanchana Bhaaskaran V. S. 2010. Asymmetrical Positive Feedback Adiabatic Logic for Low Power and Higher Frequency. International Conference on Advances in Recent Technologies in Communication and Computing. (2010), 5-9.
  11. A Vetuli, S D Pascoli and L M Reyneri, 1996. Positive feedback in adiabatic logic. Electronics Letters. (26th September 1996) Vol. 32 No. 20, 1867- 1869
  12. Kevin Nowka. 2012. Circuits Design for Low Power. IBM Austin Research Laboratory, university of texas – ppt. users. ece. utexas. edu/~adnan/vlsi-07/nowka-low-power-07. pp (dated 02 dec 2012)
  13. Massoud Pedram. 1995. Design Technologies for Low Power VLSI. To appear in Encyclopedia of Computer Science and Technology (1995).
  14. R Jacob Baker, Harry W. Li, David E Boyce. CMOS Circuit Design, layout and Simulation. IEEE Press series, Prentice Hall of India Pvt Ltd
  15. S. M. Kang, Yusuf Leblebici. 2003. CMOS Digital Integrated Circuits Analysis and Design. chapter 7, Tata McGraw Hill Education Private Ltd. , Third edition2003, 274-307
  16. Neil H. E. Weste and David Harris. CMOS VLSI Design: A Circuits and Systems Perspective. chapter 6, section 6. 2. 5. 2, Pearson, 236
  17. Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. 2003. Digital Integrated Circuits A Design Perspective. (January 3, 2003 chapter 3, Prentice Hall; 2 edition.
Index Terms

Computer Science
Information Sciences

Keywords

CPLAG DPETDFF XOR FAL SAL PDP