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Modified CPL Adiabatic Gated Logic – MCPLAG based DPET DFF with XOR

by Manoj Sharma, Arti Noor
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 89 - Number 19
Year of Publication: 2014
Authors: Manoj Sharma, Arti Noor
10.5120/15743-4701

Manoj Sharma, Arti Noor . Modified CPL Adiabatic Gated Logic – MCPLAG based DPET DFF with XOR. International Journal of Computer Applications. 89, 19 ( March 2014), 35-41. DOI=10.5120/15743-4701

@article{ 10.5120/15743-4701,
author = { Manoj Sharma, Arti Noor },
title = { Modified CPL Adiabatic Gated Logic – MCPLAG based DPET DFF with XOR },
journal = { International Journal of Computer Applications },
issue_date = { March 2014 },
volume = { 89 },
number = { 19 },
month = { March },
year = { 2014 },
issn = { 0975-8887 },
pages = { 35-41 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume89/number19/15743-4701/ },
doi = { 10.5120/15743-4701 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:09:43.305594+05:30
%A Manoj Sharma
%A Arti Noor
%T Modified CPL Adiabatic Gated Logic – MCPLAG based DPET DFF with XOR
%J International Journal of Computer Applications
%@ 0975-8887
%V 89
%N 19
%P 35-41
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The use of Adiabatic Logic in VLSI chip design has certainly promised positive aspects in terms of optimizing the power equations. In the reported work authors have extended their proposed CPLAG based 'XOR' implementation. The modified 'XOR' implementation is further configured to implement a dynamic positive edge triggered D flip flop. Both the reported circuits are functionally verified and found to be satisfactory to a high degree of signal integrity and accuracy. DFF circuit is further examined with different load, temperature range, transistor size and voltage levels. The results obtained from the proposed implementation of hybrid 'XOR' and DFF have showed good results. The average power at 1. 5V, 180nm, 25oC, 1fF load is 0. 209nW and 23-39nW for 0. 8v, 40oC for different run with Pclk_Q delay 0. 2ns, input_Q delay 16µs, Qtrise 44. 6µs, Qtfall 61µs, Qbtrise 4. 54µs, Qbtfall 3µs with 50. 9 zepto units PDP. The average power consumption for a conventional semi-adiabatic PFAL DFF is 35mW approx as compared to 0. 1µW for the implemented DFF.

References
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Index Terms

Computer Science
Information Sciences

Keywords

CPLAG DPETDFF XOR FAL SAL PDP