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Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology

International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 89 - Number 20
Year of Publication: 2014
Varika Pandey
Shyam Akashe

Varika Pandey and Shyam Akashe. Article: Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology. International Journal of Computer Applications 89(20):11-18, March 2014. Full text available. BibTeX

	author = {Varika Pandey and Shyam Akashe},
	title = {Article: Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {89},
	number = {20},
	pages = {11-18},
	month = {March},
	note = {Full text available}


Reduction of power dissipation is one of the most important challenges in VLSI circuit design. Due to scaling, sub threshold leakage current plays a dominant role in total power dissipation. This paper illustrates application of power saving SVL technique on 2:1 NAND MUX architecture. This application offers significant reduction in leakage power and leakage current viz-a-viz previous techniques. Self controllable Voltage Level Circuit (SVL) technique drastically reduces stand by leakage power and leakage current of CMOS logic circuits. This technique compare the optimization of leakage current and leakage power using two different design of 2:1 MUX. First is conventional MUX and other one is NAND based 2:1 MUX. The performance of this designed circuit is realized on a standard 45nm technology by using 0. 7v supply voltage. It is easily concluded that this 2:1 nand based MUX achieves 651. 9 Pw leakage power (Pst) and leakage current 1. 020nA in standby mode, Where as conventional MUX achieved 2. 04nA leakage current and 0. 5nW leakage power.


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