CFP last date
20 August 2024
Call for Paper
September Edition
IJCA solicits high quality original research papers for the upcoming September edition of the journal. The last date of research paper submission is 20 August 2024

Submit your paper
Know more
Reseach Article

Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology

by Varika Pandey, Shyam Akashe
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 89 - Number 20
Year of Publication: 2014
Authors: Varika Pandey, Shyam Akashe
10.5120/15746-4512

Varika Pandey, Shyam Akashe . Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology. International Journal of Computer Applications. 89, 20 ( March 2014), 11-18. DOI=10.5120/15746-4512

@article{ 10.5120/15746-4512,
author = { Varika Pandey, Shyam Akashe },
title = { Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology },
journal = { International Journal of Computer Applications },
issue_date = { March 2014 },
volume = { 89 },
number = { 20 },
month = { March },
year = { 2014 },
issn = { 0975-8887 },
pages = { 11-18 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume89/number20/15746-4512/ },
doi = { 10.5120/15746-4512 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:09:44.690202+05:30
%A Varika Pandey
%A Shyam Akashe
%T Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 89
%N 20
%P 11-18
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Reduction of power dissipation is one of the most important challenges in VLSI circuit design. Due to scaling, sub threshold leakage current plays a dominant role in total power dissipation. This paper illustrates application of power saving SVL technique on 2:1 NAND MUX architecture. This application offers significant reduction in leakage power and leakage current viz-a-viz previous techniques. Self controllable Voltage Level Circuit (SVL) technique drastically reduces stand by leakage power and leakage current of CMOS logic circuits. This technique compare the optimization of leakage current and leakage power using two different design of 2:1 MUX. First is conventional MUX and other one is NAND based 2:1 MUX. The performance of this designed circuit is realized on a standard 45nm technology by using 0. 7v supply voltage. It is easily concluded that this 2:1 nand based MUX achieves 651. 9 Pw leakage power (Pst) and leakage current 1. 020nA in standby mode, Where as conventional MUX achieved 2. 04nA leakage current and 0. 5nW leakage power.

References
  1. "A low leakage current power 180nm CMOS SRAM"2008 IEEE
  2. S. Mutohetal, "A 1V multithreshold voltages CMOS DSP with an efficient power management technique for ,mobile phone applications" Diegest of technical paper, International solid state circuits conference (ISSCC'96), FA 10. 4, PP168-169, 438, Feb 1996
  3. T. Kuroda et al. , "A 0. 9 V 150 MHz,10Mw, 4mm2, 2 D discrete cosine transform core processor with variable threshold- voltage (Vt) scheme" IEEE jour. , of solid state circuits, vol 31,no 11,pp,1770-1779,Nov 1996
  4. H. Mizuno and T Nagano " Driving source- line cell architecture for sub -1V high-speed low voltage applications" circuits, IEEE journal of solid-state circuits ,vol 31,no4, pp 552-557, april 1996.
  5. J. Kao and A. P. Chandrakasan, "Dual-Threshold voltage Technique for low power digital circuits", IEEE journal of solid state circuits, vol 35,no, 7,july 2000.
  6. K. Roy, S Mukhopadhyay and "leakage reduction techniques in deepsubmicrometer CMOS circuits," Proc. IEEE, vol, 91,no,2, ,pp 305-327 ,feb. 2003.
  7. Mohab Anis , Shawki and Mohamed Elmasry, "Design and optimization of multi threshold CMOS (MTCMOS) circuits" IEEE transaction on computer aided design of integrated circuits and systems ,vol 22, no . 10, p. p,1324-1324 oct 2003
  8. J. Halter and F. Najm , " A gate-level leakage power reduction method for ultra low power CMOS circuits," in proc. IEEE custom integrated circuits conf, santa clara , CA, 1997 , pp . 475-478.
  9. Intel Inc. , Santa Clara, CA, "Intel XScale," 2010. [Online]. Available:http://www. intel. com/design/intelxscale
  10. IBM Corp. , New York, "IBM Power PC," 2010. [Online]. Available:http://www. chips. ibm. com/products/powerpc
  11. A. Wang and A. Chandrakasan, "A 180-mV sub threshold FFT processor using a minimum energy design methodology," IEEE J. Solid- State Circuits, vol. 40, no. 1, pp. 310–319, Jan. 2005.
  12. G. Chen, M. Fojtik, D. Kim, D. Fick, J. Park, M. Seok, M. -T. Chen, Z. Foo, D. Sylvester, and D. Blaauw, "Millimeter- scale nearly perpetual sensor system with stacked battery and solar cells," in Proc. ISSCC,2010, pp. 288–289.
  13. J. Kwong, Y. Ramadass, N. Verma, M. Koesler, K. Huber, H. Moormann, and A. Chandrakasan, "A 65 nm sub-Vt crocontroller with integrated SRAM and switched-capacitor DC-DC converter," in Proc. ISSCC, 2008, pp. 282–285.
  14. B. Zhai, L. Nazhadili, J. Olson, A. Reeves, M. Minuth, R. Helfand, S. Pant, D. Blaauw, and T. Austin, "A 2. 60 pJ/Inst sub threshold sensor processor for optimal energy efficiency," in Proc. Symp. VLSI Circuits,2006, pp. 154–155.
  15. L. Chang et al. , "Stable SRAM Cell Design for the 32nm Node and Beyond," Symp. VLSI Tech. Dig. , pp. 292-293, Jun. , 2005.
  16. Rafik S. Guindi , Farid N. Najm, Design Techniques for Gate-Leakage Reduction in CMOS Circuits, Proceedings of the Fourth International Symposium on Quality Electronic Design, p. 61, March 24-26, 2003.
  17. M. D. Powell, S. H. Yang, B. Falsafi etal. . Gated – VDD:A circuit technique to reduce leakage in cache memories. In proceedings of International Symposium on Low Power Electronics and Design, July 2000
  18. Amit Agarwal, Hai Li and Kaushik Roy. DRG Cache: A data retention gated- ground cache for low power. In proceedings of the 34th Design Automation Conference, June 2002.
  19. Amit Agarwal, Hai Li, and Kaushik Roy, "DRG-Cache: A data retention gated-ground cache for low power", Proceedings of the 39th Design Automation Conference, June 2002
  20. J. Rodrigues, O. C. Akgun, and V. Owall, "A <1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS," in Proc. VLSI-SoC, June 2010.
  21. O. Akgun, J. Rodrigues, Y. Leblebici, and V. Owall, "High-level energy estimation in the sub-VT domain: Simulation and measurement of a cardiac event detector," IEEE Trans. Biomed. Circuits Syst. , accepted for publication
Index Terms

Computer Science
Information Sciences

Keywords

SVL LSVL USVL Stand- by mode