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A Load Balancer for a Multi-Stage Router Architecture

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International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 89 - Number 3
Year of Publication: 2014
Authors:
Shadi Atalla
Andrea Bianco
Robert Birke
Luca Giraudo
10.5120/15479-4193

Shadi Atalla, Bianco, Robert Birke and Luca Giraudo. Article: A Load Balancer for a Multi-Stage Router Architecture. International Journal of Computer Applications 89(3):1-7, March 2014. Full text available. BibTeX

@article{key:article,
	author = {Shadi Atalla and andrea Bianco and Robert Birke and Luca Giraudo},
	title = {Article: A Load Balancer for a Multi-Stage Router Architecture},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {89},
	number = {3},
	pages = {1-7},
	month = {March},
	note = {Full text available}
}

Abstract

Multi-stage software router architectures permit to overcome several limitations inherent to single stage software routers. One of the key elements of the multi-stage architecture under study are the load balancers, which are used to distribute the load among backend routers. However, using a PC (Personal Computer) as a load balancer could create a performance bottleneck in the overall architecture. Since the operations performed by the load balancer are simple, we explore the possibility of an hardware-based implementation of load balancing functionality with the goal of improving its performance. In this paper, we describe the architecture of an FPGA-based load balancer and we present some performance results of its prototype implementation.

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