Call for Paper - November 2023 Edition
IJCA solicits original research papers for the November 2023 Edition. Last date of manuscript submission is October 20, 2023. Read More

A Load Balancer for a Multi-Stage Router Architecture

International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 89 - Number 3
Year of Publication: 2014
Shadi Atalla
Andrea Bianco
Robert Birke
Luca Giraudo

Shadi Atalla, Bianco, Robert Birke and Luca Giraudo. Article: A Load Balancer for a Multi-Stage Router Architecture. International Journal of Computer Applications 89(3):1-7, March 2014. Full text available. BibTeX

	author = {Shadi Atalla and andrea Bianco and Robert Birke and Luca Giraudo},
	title = {Article: A Load Balancer for a Multi-Stage Router Architecture},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {89},
	number = {3},
	pages = {1-7},
	month = {March},
	note = {Full text available}


Multi-stage software router architectures permit to overcome several limitations inherent to single stage software routers. One of the key elements of the multi-stage architecture under study are the load balancers, which are used to distribute the load among backend routers. However, using a PC (Personal Computer) as a load balancer could create a performance bottleneck in the overall architecture. Since the operations performed by the load balancer are simple, we explore the possibility of an hardware-based implementation of load balancing functionality with the goal of improving its performance. In this paper, we describe the architecture of an FPGA-based load balancer and we present some performance results of its prototype implementation.


  • Foundry serveriron load balancer.
  • Hardware Load Balancer for Multi-Stage Software Router. http://opencores. org/project,loadbalancer.
  • Microsofts network load balancing. http:// www. foundrynet. com/products/webswitches/ serveriron/.
  • NetFPGA. http://www. netfpga. org/.
  • Katerina Argyraki, Salman Baset, Byung-Gon Chun, Kevin Fall, Gianluca Iannaccone, Allan Knies, Eddie Kohler, Maziar Manesh, Sergiu Nedevschi, and Sylvia Ratnasamy. Can software routers scale? In PRESTO, Seattle, USA, Aug. 2008.
  • Shadi Atalla, Andrea Bianco, Robert Birke, and Luca Giraudo. NetFPGA-based load balancer for a Multi-Stage router architecture. In International Conference on Computer Information Systems 2014 (ICCIS-2014), Hammamet, Tunisia, January 2014.
  • Shadi Atalla, Davide Cuda, Paolo Giaccone, and Marco Pretti. Belief-propagation-assisted scheduling in inputqueued switches. IEEE Transactions on Computers, 62(10):2101–2107, 2013.
  • A. Bianco, R. Birke, J. M. Finochietto, L. Giraudo, F. Marenco, M. Mellia, A. Khan, and D. Manjunath. Control and management plane in a multi-stage software router architecture. In HPSR, Shanghai, China, May 2008.
  • A. Bianco, J. M. Finochietto, G. Galante, M. Mellia, D. Mazzucchi, and F. Neri. Scalable layer-2/layer-3 multistage switching architectures for software routers. In IEEE GLOBECOM, San Francisco, USA, Dec. 2006.
  • A. Bianco, J. M. Finochietto, M. Mellia, F. Neri, and G. Galante. Multistage switching architectures for software routers. IEEE Network, 21(4):15–21, Jul. -Aug. 2007.
  • Andrea Bianco, Robert Birke, Fikru Getachew Debele, and Luca Giraudo. Snmp management in a distributed software router architecture. In Communications (ICC), 2011 IEEE International Conference on, pages 1–5. IEEE, 2011.
  • Andrea Bianco, Robert Birke, Luca Giraudo, and Nanfang Li. Multistage software routers in a virtual environment. In Global Telecommunications Conference (GLOBECOM 2010), 2010 IEEE, pages 1–5. IEEE, 2010.
  • Raffaele Bolla and Roberto Bruschi. RFC 2544 performance evaluation and internal measurements for a Linux-based open router. In HPSR, Poznan, Poland, Jun. 2006.
  • Raffaele Bolla and Roberto Bruschi. An effective forwarding architecture for SMP Linux routers. In IT-NEWS, Venice, Italy, Feb. 2008.
  • Raffaele Bolla and Roberto Bruschi. PC-based software routers: High performance and application service support. In PRESTO, Seattle, USA, Aug. 2008.
  • Mihai Dobrescu, Norbert Egi, Katerina Argyraki, Byung-Gon Chun, Kevin Fall, Gianluca Iannaccone, Allan Knies, Maziar Manesh, and Sylvia Ratnasamy. RouteBricks: exploiting parallelism to scale software routers. In SOSP, Big Sky, USA, Oct. 2009.
  • Nikhil Handigol, Srinivasan Seetharaman, Nick McKeown, and Ramesh Johari. Plug-n-serve: Load-balancing web traffic using openflow, 2009.
  • IETF. Forwarding and control element separation working group (ForCES). http://tools. ietf. org/wg/forces/.
  • A. J. Khan, R. Birke, D. Manjunath, A. Sahoo, and A. Bianco. Distributed PC based routers: bottleneck analysis and architecture proposal. In HPSR, Shanghai, China, May 2008.
  • Marc K¨orner, Herbert Almus, Hagen Woesner, and Tobias Jungel. Metrics and measurement tools in openflow and the ofelia testbed. In Measurement Methodology and Tools, pages 127–138. Springer, 2013.
  • Ian Kuon, Russell Tessier, and Jonathan Rose. Fpga architecture: Survey and challenges. Foundations and Trends R in Electronic Design Automation, 2(2):135–253, 2008.
  • David C. Plummer. RFC 826, ethernet address resolution protocol, Nov. 1982. http://www. ietf. org/rfc/rfc0826. txt.
  • Q Xu, H Rastegarfar, Y Ben M'Sallem, A Leon-Garcia, S LaRochelle, and LA Rusch. Analysis of large-scale multistage all-optical packet switching routers. Optical Communications and Networking, IEEE/OSA Journal of, 4(5):412– 425, 2012.