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Reseach Article

A Load Balancer for a Multi-Stage Router Architecture

by Shadi Atalla, andrea Bianco, Robert Birke, Luca Giraudo
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 89 - Number 3
Year of Publication: 2014
Authors: Shadi Atalla, andrea Bianco, Robert Birke, Luca Giraudo
10.5120/15479-4193

Shadi Atalla, andrea Bianco, Robert Birke, Luca Giraudo . A Load Balancer for a Multi-Stage Router Architecture. International Journal of Computer Applications. 89, 3 ( March 2014), 1-7. DOI=10.5120/15479-4193

@article{ 10.5120/15479-4193,
author = { Shadi Atalla, andrea Bianco, Robert Birke, Luca Giraudo },
title = { A Load Balancer for a Multi-Stage Router Architecture },
journal = { International Journal of Computer Applications },
issue_date = { March 2014 },
volume = { 89 },
number = { 3 },
month = { March },
year = { 2014 },
issn = { 0975-8887 },
pages = { 1-7 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume89/number3/15479-4193/ },
doi = { 10.5120/15479-4193 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:08:16.024478+05:30
%A Shadi Atalla
%A andrea Bianco
%A Robert Birke
%A Luca Giraudo
%T A Load Balancer for a Multi-Stage Router Architecture
%J International Journal of Computer Applications
%@ 0975-8887
%V 89
%N 3
%P 1-7
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Multi-stage software router architectures permit to overcome several limitations inherent to single stage software routers. One of the key elements of the multi-stage architecture under study are the load balancers, which are used to distribute the load among backend routers. However, using a PC (Personal Computer) as a load balancer could create a performance bottleneck in the overall architecture. Since the operations performed by the load balancer are simple, we explore the possibility of an hardware-based implementation of load balancing functionality with the goal of improving its performance. In this paper, we describe the architecture of an FPGA-based load balancer and we present some performance results of its prototype implementation.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Load Balancer