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VLSI Implementation of Segmentation of Single Channel ECG

International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 90 - Number 13
Year of Publication: 2014
S. Preethi
M. Jayasheela

S.preethi and M.jayasheela. Article: VLSI Implementation of Segmentation of Single Channel ECG. International Journal of Computer Applications 90(13):27-30, March 2014. Full text available. BibTeX

	author = {S.preethi and M.jayasheela},
	title = {Article: VLSI Implementation of Segmentation of Single Channel ECG},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {90},
	number = {13},
	pages = {27-30},
	month = {March},
	note = {Full text available}


In this paper the implementation of extraction of respiratory signal from ECG signal in very large scale integration (VLSI) using discrete wavelet transform (DWT) is discussed. The Indirect method to obtain the respiratory signal from ECG can benefit both respiratory and cardiac activities. The accuracy of the extracted respiratory signal will be high. The implementation is based on bit serial approach (BS) which substitute multiply and accumulate operations. BS provides a multiplication-free method for calculating inner products of fixed-point data. But increase in filter order leads complexity. Here we propose high-speed and low power architecture. The proposed method is implemented in hardware description language and verified via simulation. The proposed architecture scheme yields significantly reduced complexity, less area and high speed features.


  • Domenico Labate, Fabio La Foresta, Gianluigi Occhiuto, Francesco Carlo Morabito, Aime Lay-Ekuakille, and Patrizia Vergallo. July 2013. Empirical Mode Decomposition vs. Wavelet Decomposition for the Extraction of Respiratory Signal from Single-Channel ECG: A Comparison, IEEE SENSORS JOURNAL, VOL. 13, NO. 7.
  • Kung. H. T 1982, Why systolic architecture? IEEE Computer 15, 37–45.
  • Yu. S and Swartzlander. E. E. 2001. DCT implementation with distributed arithmetic, IEEE Transactions on Computers 50 (9) 985–991.
  • Hanho Lee and Gerald E. Sobelman. 2002. FPGA-based digit-serial CSD FIR ?lter for image signal format conversion, Microelectronics Journal 33 (5–6) 501–508.
  • Valeria Garofalo. 2008. Fixed-width multipliers for the implementation of efficient digital FIR ?lters, Microelectronics Journal 39 (12) 1491–1498.
  • Lei Zhang and Tadeusz Kwasniewski. 2009 FIR ?lter optimization using bit-edge equalization in high-speed backplane BSta transmission, Microelectronics Journal 40 (10) 1449–1457.
  • Eshtawie. M. A. M and Othman. M. 2006 On-line BS-LUT architecture for high-speed high-order digital FIR ?lters, in: Proceedings of the IEEE International Conference on Communication Systems (ICCS), Singapore.
  • Choi. J. P, Shin. S. C, and Chung. J. G. 2000 Ef?cient ROM size reduction for distributed arithmetic, in: Proceedings of the IEEE International Symposium Circuits Systems (ISCAS), pp. 61–64.
  • Sanjay, Attri B. S, Sohi, and Chopra. Y. C. 2001. Ef?cient design of application speci?c DSP cores using FPGAs, in: International Conference on ASIC Proceedings, pp. 462-466.
  • Kim Kyung-Saeng and Kwyro Lee. 2003 Low-power and area efficient FIR ?lter implementation suitable for multiple tape, IEEE Transactions on VLSI Systems 11 (1).
  • Antonion. A. 1993 Digital Filters: Analysis, Design, and Applications, McGraw-Hill, New York.
  • Labate. D, La Foresta. F, Inuso. G, and Morabito. F. C. 2011 "Remarks about Wavelet Analysis in the EEG Artifacts Detection," in Frontiers in Artificial Intelligence and Application, vol. 226. Amsterdam, The Netherlands: IOS Press, pp. 99–106.
  • Mallat. S. 1999. A Wavelet Tour of Signal Processing. New York, NY, USA: Academic Press.
  • Percival. D. B and Walden. A. D. 2000 Wavelet Methods for Time Series Analysis. Cambridge, U. K. : Cambridge Univ. Press.