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Design of a Specific Instructions Set Processor for AES Algorithm

by Karim Shahbazi, Mohammad Eshghi
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 93 - Number 4
Year of Publication: 2014
Authors: Karim Shahbazi, Mohammad Eshghi
10.5120/16205-5496

Karim Shahbazi, Mohammad Eshghi . Design of a Specific Instructions Set Processor for AES Algorithm. International Journal of Computer Applications. 93, 4 ( May 2014), 36-40. DOI=10.5120/16205-5496

@article{ 10.5120/16205-5496,
author = { Karim Shahbazi, Mohammad Eshghi },
title = { Design of a Specific Instructions Set Processor for AES Algorithm },
journal = { International Journal of Computer Applications },
issue_date = { May 2014 },
volume = { 93 },
number = { 4 },
month = { May },
year = { 2014 },
issn = { 0975-8887 },
pages = { 36-40 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume93/number4/16205-5496/ },
doi = { 10.5120/16205-5496 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:14:58.542122+05:30
%A Karim Shahbazi
%A Mohammad Eshghi
%T Design of a Specific Instructions Set Processor for AES Algorithm
%J International Journal of Computer Applications
%@ 0975-8887
%V 93
%N 4
%P 36-40
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, a new architecture for Advanced Encryption Standard (AES) Algorithm based on Application Specific Instruction set Processors (ASIP) design technique is proposed. The basic configuration is developed in order to reduce the execution clock pulses for the main specific instructions. According to the improvement of the first register configuration, two ASIPs are designed for AES algorithm. The second ASIP is 89% faster and have 22% less gates than the first proposed design.

References
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Index Terms

Computer Science
Information Sciences

Keywords

ASIP AES algorithm RTL crypto Processor

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