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Reseach Article

High-Resolution CMOS Counter Type ADC Layout Design by using Transmission Gate Logic

by Lucky Prajapati, Teena Raikwar, Puran Gour
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 95 - Number 23
Year of Publication: 2014
Authors: Lucky Prajapati, Teena Raikwar, Puran Gour
10.5120/16731-5665

Lucky Prajapati, Teena Raikwar, Puran Gour . High-Resolution CMOS Counter Type ADC Layout Design by using Transmission Gate Logic. International Journal of Computer Applications. 95, 23 ( June 2014), 1-3. DOI=10.5120/16731-5665

@article{ 10.5120/16731-5665,
author = { Lucky Prajapati, Teena Raikwar, Puran Gour },
title = { High-Resolution CMOS Counter Type ADC Layout Design by using Transmission Gate Logic },
journal = { International Journal of Computer Applications },
issue_date = { June 2014 },
volume = { 95 },
number = { 23 },
month = { June },
year = { 2014 },
issn = { 0975-8887 },
pages = { 1-3 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume95/number23/16731-5665/ },
doi = { 10.5120/16731-5665 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:20:10.671194+05:30
%A Lucky Prajapati
%A Teena Raikwar
%A Puran Gour
%T High-Resolution CMOS Counter Type ADC Layout Design by using Transmission Gate Logic
%J International Journal of Computer Applications
%@ 0975-8887
%V 95
%N 23
%P 1-3
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, we propose counter type ADC for high-speed applications. Counter type ADCs are one of the most popular ADC topology used to implement moderate resolution converter due to their reasonably fast conversion time and simplicity. . Designed ADC has 8 input channels each of which has 0 – 2. 6 V signal range. The resolution of ADC the converter is 8 bits. The amount of passing through a system from input to output ADCs can be increased by using its technique This is implemention on the circuit level with pass transistor circuit. The primary focus of this work design and implementation of a pass transistor based Analog-to-Digital converter. The proposed counter type ADC is composed of a 8-bit DAC design by using transmission gate logic, a comparator logic , 8 bit digital counter and "AND" gates to pass the clock signal by considering the chip area, operation speed, and circuit complexity.

References
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  3. Lucky prajapati, Prof. Teena Raikar, Prof Puran Gour " CMOS Layout Design for Low Power Counter Type Analog to Digital Converter" Review Paper " International Journal of Engineering Universe for Scientific Research and Management (EUSRM) ISSN: 2319-3069, Vol. 6, Issue 1
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Index Terms

Computer Science
Information Sciences

Keywords

High-Resolution CMOS