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Implementation of USB 3.0 SuperSpeed Physical Layer using Verilog HDL

by Hardik Trivedi, Rohit Kumar, Ronak Tank, Sundaresan C., Madhushankara M.
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 95 - Number 24
Year of Publication: 2014
Authors: Hardik Trivedi, Rohit Kumar, Ronak Tank, Sundaresan C., Madhushankara M.
10.5120/16739-6571

Hardik Trivedi, Rohit Kumar, Ronak Tank, Sundaresan C., Madhushankara M. . Implementation of USB 3.0 SuperSpeed Physical Layer using Verilog HDL. International Journal of Computer Applications. 95, 24 ( June 2014), 1-5. DOI=10.5120/16739-6571

@article{ 10.5120/16739-6571,
author = { Hardik Trivedi, Rohit Kumar, Ronak Tank, Sundaresan C., Madhushankara M. },
title = { Implementation of USB 3.0 SuperSpeed Physical Layer using Verilog HDL },
journal = { International Journal of Computer Applications },
issue_date = { June 2014 },
volume = { 95 },
number = { 24 },
month = { June },
year = { 2014 },
issn = { 0975-8887 },
pages = { 1-5 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume95/number24/16739-6571/ },
doi = { 10.5120/16739-6571 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:20:16.135980+05:30
%A Hardik Trivedi
%A Rohit Kumar
%A Ronak Tank
%A Sundaresan C.
%A Madhushankara M.
%T Implementation of USB 3.0 SuperSpeed Physical Layer using Verilog HDL
%J International Journal of Computer Applications
%@ 0975-8887
%V 95
%N 24
%P 1-5
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this proposed design it mainly includes USB 3. 0, Physical Layer along with USB 2. 0 functionality with Super speed functionality. Physical Layer mainly contains PCI Express and PIPE interface. This proposed design transferred data from transmitter to receiver serially. This design manages to transfer data either on 2. 5GT/s or on 5. 0GT/s depends upon the mode and rate. The design generates clock that runs on two different frequencies i. e. 125MHz and 250MHz that used to transfer data on parallel interface. This Design manages to capture the data that are coming asynchronously and lock the receiver clock with incoming asynchronous serial data. The architecture for USB 3. 0 Physical Layer has been proposed in this paper. The proposed model is implemented and verified using Verilog HDL.

References
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  2. "Data Manual Texas Instruments" , Literature number: SLLSE16E, June 3, 2011
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  5. "PHY interface for the PCI Express and USB 3. 0 Architecture", March 11, 2009.
  6. "Lattice Semiconductor Corporation 8b/10b Encoder/Decoder", February 2012.
  7. Ching-Che Chung, Chen-Yi Lee, "An All-Digital Phase Locked Loop for high speed clock generation", Febr 6, 2003.
  8. Clifford E. Cummings and Peter Alfke, "Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons", SNUG 2002.
  9. Ravi Budruk, Don Anderson & Tom Sanely, 2004. "PCI Express System Architecture", Mindshare Inc. , pp 419-434.
  10. Thatcher, Jonathan (1996-04-01). "Thoughts on Gigabit Ethernet Physical", IBM Retrieved on 2008-08-17.
  11. Jenming Wu & Yu-Ho Hsu, "8B/10B Codec for Efficient PAPR Re-duction in OFDM Communication Systems", International technology roadmap for Semiconductors (ITRS).
Index Terms

Computer Science
Information Sciences

Keywords

Implementation USB

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