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Ancient Indian Vedic Mathematics based 32-Bit Multiplier Design for High Speed and Low Power Processors

by Nishant G. Deshpande, Rashmi Mahajan
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 95 - Number 24
Year of Publication: 2014
Authors: Nishant G. Deshpande, Rashmi Mahajan
10.5120/16742-6956

Nishant G. Deshpande, Rashmi Mahajan . Ancient Indian Vedic Mathematics based 32-Bit Multiplier Design for High Speed and Low Power Processors. International Journal of Computer Applications. 95, 24 ( June 2014), 19-22. DOI=10.5120/16742-6956

@article{ 10.5120/16742-6956,
author = { Nishant G. Deshpande, Rashmi Mahajan },
title = { Ancient Indian Vedic Mathematics based 32-Bit Multiplier Design for High Speed and Low Power Processors },
journal = { International Journal of Computer Applications },
issue_date = { June 2014 },
volume = { 95 },
number = { 24 },
month = { June },
year = { 2014 },
issn = { 0975-8887 },
pages = { 19-22 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume95/number24/16742-6956/ },
doi = { 10.5120/16742-6956 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:20:18.179437+05:30
%A Nishant G. Deshpande
%A Rashmi Mahajan
%T Ancient Indian Vedic Mathematics based 32-Bit Multiplier Design for High Speed and Low Power Processors
%J International Journal of Computer Applications
%@ 0975-8887
%V 95
%N 24
%P 19-22
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The use of Vedic mathematics lies in the fact that it reduces the typical calculation in the conventional mathematics to very simple once. This is so because the Vedic formulae have claimed to be building on the natural principles on which the human mind works. Vedic mathematics is a several effective algorithms, which has spread over to various branches of engineering such as computing. In computers, typical central processing unit devotes a considerable amount of processing time in implementing arithmetic operations, particularly multiplication operation. In this work, I have studied different multipliers, which give low power requirement and high speed, also give information of "urdhva-Tiryabhyam" algorithm of ancient Indian Vedic mathematics, which has utilized for multiplication to improve speed of multipliers. The proposed algorithm has modeled using VHDL, a hardware descriptive language. In a work I have simulated and synthesized 32-bit multiplier, the result shows that multiplier implemented using Vedic multiplication is efficient in terms of speed.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Vedic Mathematics Multiplier Urdhva-Tiryabhyam

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