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High Performance Implementation of Universal Gate using Low Power Source Gating Technique

International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 96 - Number 10
Year of Publication: 2014
Harmeet Singh Arora
Rohan Kochar
Geetanjali Sharma

Harmeet Singh Arora, Rohan Kochar and Geetanjali Sharma. Article: High Performance Implementation of Universal Gate using Low Power Source Gating Technique. International Journal of Computer Applications 96(10):26-31, June 2014. Full text available. BibTeX

	author = {Harmeet Singh Arora and Rohan Kochar and Geetanjali Sharma},
	title = {Article: High Performance Implementation of Universal Gate using Low Power Source Gating Technique},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {96},
	number = {10},
	pages = {26-31},
	month = {June},
	note = {Full text available}


Area, Speed and Cost were used to be the main concerns in the VLSI industry and Power consumption was the secondary consideration. But, nowadays, Power is given equal importance as area and speed. The increasing demand for mobile electronic devices which require complex functionality and high speed has increased the requirement for power efficient VLSI circuits. Since, a large number of transistors are being packed onto a single chip, the increase in operating frequency and processing capacity results in increased power dissipation. Power dissipation plays an important role in VLSI circuits since it not only causes overheating which reduces chip life but also makes it difficult to use devices in a portable environment [1]. Also, it results in waste of energy in form of heat which is obviously a major concern nowadays.


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