Call for Paper - January 2023 Edition
IJCA solicits original research papers for the January 2023 Edition. Last date of manuscript submission is December 20, 2022. Read More

Reconfigurable Adder Architectures for Low Power Applications

International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 96 - Number 4
Year of Publication: 2014
S. Karthick
S. Valarmathy
E. Prabhu

S Karthick, S Valarmathy and E Prabhu. Article: Reconfigurable Adder Architectures for Low Power Applications. International Journal of Computer Applications 96(4):31-36, June 2014. Full text available. BibTeX

	author = {S. Karthick and S. Valarmathy and E. Prabhu},
	title = {Article: Reconfigurable Adder Architectures for Low Power Applications},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {96},
	number = {4},
	pages = {31-36},
	month = {June},
	note = {Full text available}


The growing design complexity has attracted the designs with Reconfigurable fabrics, where adaptable fabrics are utilized to solve the computational problems. Reconfigurable computing provides the flexibility in arriving at the problem specific architectures which helps in improving the performance due to custom approach. In this paper, a flexible reconfigurable architecture with different adder variants like Ripple Carry, Carry Look-ahead, Carry Select and Carry Bypass adders are implemented to form dynamically reconfigurable Hybrid adder architectures. Such hybrid architectures are utilized for the applications where design constraints are only for low power or high performance or the low area or sometimes a balanced design metrics. The design was modelled using Verilog HDL and synthesized in Synopsys Design Compiler by mapping to TSMC 65nm technology node. Standard ASIC design methodologies are considered to bench mark the results. The proposed architecture enables the designer to perform efficient Design Space Exploration. The design can be made adaptable to any of the reconfigurable processor and a similar improvement can be obtained. The proposed architectures results in 18-54% reduced power consumption when designed with various combinations of reconfigurable adder architectures and also accounted for 14-44% of area reduction.


  • Agarwal, M. ; Agrawal, N. ; Alam, M. A. , "A new design of low power high speed hybrid CMOS full adder," Signal Processing and Integrated Networks (SPIN), International Conference on , vol. , no. , pp. 448,452, 20-21 Feb. 2014
  • Moghaddam, M. ; Ghaznavi-Ghoushchi, M. B. , "A new low power-delay-product, low-area, parallel prefix adder with reduction of graph energy," Electrical Engineering (ICEE), 2011 19th Iranian Conference on , vol. , no. , pp. 1,6, 17-19 May 2011
  • Eshtawie, M. A. M. ; Hussin, S. H. S. ; Othman, M. , "Analysis of results obtained with a new proposed low area low power high speed fixed point adder," Semiconductor Electronics (ICSE), 2010 IEEE International Conference on , vol. , no. , pp. 127,130, 28-30 June 2010
  • Perri, S. ; Corsonello, P; Cocorullo, G. , "A high-speed energy-efficient 64-bit reconfigurable binary adder," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 11, no. 5, pp. 939,943, Oct. 2003
  • Chetan Kumar, V. ; Sai Phaneendra, P; Ershad Ahmed, S. ; Veeramachaneni, S. ; Moorthy Muthukrishnan, N. ; Srinivas, M. B. , "A Prefix Based Reconfigurable Adder," VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on , vol. , no. , pp. 349,350, 4-6 July 2011
  • Megalingam, R. K. ; Popuri, G. ; Ravisankar, P. , "Low Power Consumption Coarse Grained Reconfigurable Adder," Computer and Electrical Engineering, 2009. ICCEE '09. Second International Conference on , vol. 2, no. , pp. 503,506, 28-30 Dec. 2009
  • Perri, S. ; Corsonello, P. Cocorullo, G, "64-bit reconfigurable adder for low power media processing," Electronics Letters , vol. 38, no. 9, pp. 397,399, 25 Apr 2002
  • Singh, Pal, et al. "Trade-offs in Designing High-Performance Digital Adder based on Heterogeneous Architecture. " International Journal of Computer Applications, 2012.
  • Katherine Compton, Scott Hauck, "An Introduction to Reconfigurable Computing", IEEE computer, April 2000.
  • Todman, T. J. ; Constantinides, G. A. ; Wilton, S. J E; Mencer, O. ; Luk, W. ; Cheung, P. Y K, "Reconfigurable computing: architectures and design methods," Computers & Digital Techniques, IEE Proceedings - , vol. 152, no. 2, pp. 193-207, Mar 2005.
  • Mirsky, E. ; DeHon, A. , "MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources," FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on , vol. , no. , pp. 157,166, 17-19 Apr 1996.
  • Chang, C. ; Wawrzynek, J. ; Brodersen, R. W. , "BEE2: a high-end reconfigurable computing system," Design & Test of Computers, IEEE , vol. 22, no. 2, pp. 114,125, Mar-Apr 2005.
  • ChandraMohan U, "High Speed Squarer", Proceedings of the 8th VLSI Design and Test Workshops, VDAT, August 2004.