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An Efficient Full Adder Design using Different Logic Styles

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International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 98 - Number 21
Year of Publication: 2014
Authors:
Nishan Singh
Mandeep Kaur
Amardeep Singh
Puneet Jain
10.5120/17310-7786

Nishan Singh, Mandeep Kaur, Amardeep Singh and Puneet Jain. Article: An Efficient Full Adder Design using Different Logic Styles. International Journal of Computer Applications 98(21):38-41, July 2014. Full text available. BibTeX

@article{key:article,
	author = {Nishan Singh and Mandeep Kaur and Amardeep Singh and Puneet Jain},
	title = {Article: An Efficient Full Adder Design using Different Logic Styles},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {98},
	number = {21},
	pages = {38-41},
	month = {July},
	note = {Full text available}
}

Abstract

The paper discusses a comparative study of full adders with various logic style of designing. Logic style affects the switching capacitance, transition activity, short circuit current and delay. Various logic styles have been compared taking full adder as a reference circuit and power dissipation and delay as reference parameters. Simulation results of all the full adders at technologies of 180nm, 90nm, 45nm of CMOS process have been provided. It is observed that less power is consumed in the Transmission based full adder than the Convention full adder and Pass Transistor full adder.

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