The week's pick
Reseach Article
SNM Analysis of 6T SRAM at 32NM and 45NM Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 98 - Number 7 |
| Year of Publication: 2014 |
| Authors: Anurag Dandotiya, Amit S. Rajput |
10.5120/17198-7398
|
Anurag Dandotiya, Amit S. Rajput . SNM Analysis of 6T SRAM at 32NM and 45NM Technique. International Journal of Computer Applications. 98, 7 ( July 2014), 30-34. DOI=10.5120/17198-7398
Abstract
In this paper we analyze the effect of SNM dependent on different parameter in read mode and write mode. We analyze SNM of different modulation like cell ratio (CR), voltage supply (Vdd), word line (WL) and bit line (BL) by spice tools using BPTM Low Power model in different technologies. We define the read margin to characterize the SRAM cells read stability. Many researchers use only 45nm technology, but we are scaling down the technologies which is more stability for the circuit. Actually stability of SRAM cell only depends on the static noise margin (SNM) and SNM is effect the stability of SRAM cell during read operation of SRAM cells.
References
- Chua-Chin Wang, Po-Ming Lee, and Kuo-Long Chen "An SRAM Design Using Dual Threshold Voltage Transistors and Low-Power Quenchers" IEEE journal of solid-state circuits, vol. 38, no. 10, october 2003.
- Chris Hyung-il Kim, Jae-Joon Kim, Student Member, IEEE, Saibal Mukhopadhyay, Student Member, IEEE, and Kaushik Roy, Fellow, IEEEA "Forward Body-Biased Low-Leakage SRAM Cache: Device, Circuit and Architecture" Considerations IEEE transactions on very large scale integration (vlsi) systems, vol. 13, no. 3, march 2005
- Shilpi Birla, R. K. Singh, Member IACSIT, and Manisha Pattnaik, "Static Noise Margin Analysis of Various SRAM Topologies", IACSIT International Journal of Engineering and Technology, Vol. 3, No. 3, June 2011.
- Andrei Pavlov & Manoj Sachdev, "CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies". Intel Corporation, University of Waterloo, 2008 Springer Science and Business Media B. V. , pp:1-202.
- Benton H. Calhoun Anantha P. Chandrakasan "Static Noise Margin Variation for Sub-threshold SRAM in 65 nm CMOS", Solid-State Circuits, IEEE Journal vol. 41, Jan. 2006, Issue 7, pp. 1673-1679.
- Koichi Takeda et al, "A Read Static Noise Margin Free SRAM cell for Low Vdd and High Speed Applications", Solidvol. 41, Jan. 2006, Issue 1 , pp. 113-121
- Simran Kaur, Ashwani Kumar "Analysis of Low Power SRAM Memory Cell using Tanner Tool" IJECT Vol. 3, Issue 1, Jan. - March 2012
- Kevin Zhang, Member, IEEE, Uddalak Bhattacharya, Zhanping Chen, Member, IEEE, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Member, IEEE, Yih Wang, Member, IEEE, B. Zheng, and Mark Bohr, Fellow, IEEE "SRAM Design on 65-nm CMOS Technology With Dynamic Sleep Transistor for Leakage Reduction" IEEE journal of solid-state circuits, vol. 40, no. 4, april 2005.
- Benton H. Calhoun Anantha P. Chandrakasan, "Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS",ESSCIRC,2005
- Rajshekhar Keerthi, Henry Chen, "Stability and Static Noise margin analysis of low power SRAM"IEEE International Instrumentation & Measurement Technology Conference, Victoria Canada, May 2008,pp-1541-1544.
Index Terms
Keywords