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Design and Analysis of High Performance Novel 3T XOR Gate based 32-bit Adder at 28nm Technology

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IJCA Proceedings on International Conference on Advances in Emerging Technology
© 2016 by IJCA Journal
ICAET 2016 - Number 4
Year of Publication: 2016
Authors:
Sherpal Kaur
Parminder Singh

Sherpal Kaur and Parminder Singh. Article: Design and Analysis of High Performance Novel 3T XOR Gate based 32-bit Adder at 28nm Technology. IJCA Proceedings on International Conference on Advances in Emerging Technology ICAET 2016(4):1-5, September 2016. Full text available. BibTeX

@article{key:article,
	author = {Sherpal Kaur and Parminder Singh},
	title = {Article: Design and Analysis of High Performance Novel 3T XOR Gate based 32-bit Adder at 28nm Technology},
	journal = {IJCA Proceedings on International Conference on Advances in Emerging Technology},
	year = {2016},
	volume = {ICAET 2016},
	number = {4},
	pages = {1-5},
	month = {September},
	note = {Full text available}
}

Abstract

In this paper, we designed and simulated a low power one bit, 8-bit and 32-bit full adder circuits namely Novel 10T, N14T, FA24T, CPL (complementary pass-transistor logic) and DPL (double pass-transistor logic). All the adders are tested by using one bit, 8-bit and 32-bit ripple carry adder architecture using Tanner EDA tool version 13. 0. The one bit Novel 10T, N14T, XOR/XNOR function technique has been used for the generation of full adders. The proposed design successfully works with the buffering circuit in the full adder design. All full adder circuits are simulated withT-SPICE using 28nm Technology with 500 Mega Hertz frequency at 0. 9 volt supply voltage. Due to lesser length requirement in the individual transistor, all the design of adders require lesser area as compared to existing design results in the tables. There is also improvement in terms of power, delay and power-delay-product (PDP).

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