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Reseach Article

Design and Analysis of High Performance Novel 3T XOR Gate based 32-bit Adder at 28nm Technology

Published on September 2016 by Sherpal Kaur, Parminder Singh
International Conference on Advances in Emerging Technology
Foundation of Computer Science USA
ICAET2016 - Number 4
September 2016
Authors: Sherpal Kaur, Parminder Singh
a2814286-c5e9-4d06-846b-da4ca99f4801

Sherpal Kaur, Parminder Singh . Design and Analysis of High Performance Novel 3T XOR Gate based 32-bit Adder at 28nm Technology. International Conference on Advances in Emerging Technology. ICAET2016, 4 (September 2016), 1-5.

@article{
author = { Sherpal Kaur, Parminder Singh },
title = { Design and Analysis of High Performance Novel 3T XOR Gate based 32-bit Adder at 28nm Technology },
journal = { International Conference on Advances in Emerging Technology },
issue_date = { September 2016 },
volume = { ICAET2016 },
number = { 4 },
month = { September },
year = { 2016 },
issn = 0975-8887,
pages = { 1-5 },
numpages = 5,
url = { /proceedings/icaet2016/number4/25896-t048/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Advances in Emerging Technology
%A Sherpal Kaur
%A Parminder Singh
%T Design and Analysis of High Performance Novel 3T XOR Gate based 32-bit Adder at 28nm Technology
%J International Conference on Advances in Emerging Technology
%@ 0975-8887
%V ICAET2016
%N 4
%P 1-5
%D 2016
%I International Journal of Computer Applications
Abstract

In this paper, we designed and simulated a low power one bit, 8-bit and 32-bit full adder circuits namely Novel 10T, N14T, FA24T, CPL (complementary pass-transistor logic) and DPL (double pass-transistor logic). All the adders are tested by using one bit, 8-bit and 32-bit ripple carry adder architecture using Tanner EDA tool version 13. 0. The one bit Novel 10T, N14T, XOR/XNOR function technique has been used for the generation of full adders. The proposed design successfully works with the buffering circuit in the full adder design. All full adder circuits are simulated withT-SPICE using 28nm Technology with 500 Mega Hertz frequency at 0. 9 volt supply voltage. Due to lesser length requirement in the individual transistor, all the design of adders require lesser area as compared to existing design results in the tables. There is also improvement in terms of power, delay and power-delay-product (PDP).

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Index Terms

Computer Science
Information Sciences

Keywords

Full Adder Ripple Carry Adder Average Power Delay Power-delay-product (pdp) Leakage Power Noise Margin.