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Reseach Article

Design and Analysis of Faster Multiplier using Vedic Mathematics Technique

Published on September 2016 by Amit Kumar, Hitesh Pahuja
International Conference on Advances in Emerging Technology
Foundation of Computer Science USA
ICAET2016 - Number 9
September 2016
Authors: Amit Kumar, Hitesh Pahuja
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Amit Kumar, Hitesh Pahuja . Design and Analysis of Faster Multiplier using Vedic Mathematics Technique. International Conference on Advances in Emerging Technology. ICAET2016, 9 (September 2016), 28-31.

@article{
author = { Amit Kumar, Hitesh Pahuja },
title = { Design and Analysis of Faster Multiplier using Vedic Mathematics Technique },
journal = { International Conference on Advances in Emerging Technology },
issue_date = { September 2016 },
volume = { ICAET2016 },
number = { 9 },
month = { September },
year = { 2016 },
issn = 0975-8887,
pages = { 28-31 },
numpages = 4,
url = { /proceedings/icaet2016/number9/25936-t150/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Advances in Emerging Technology
%A Amit Kumar
%A Hitesh Pahuja
%T Design and Analysis of Faster Multiplier using Vedic Mathematics Technique
%J International Conference on Advances in Emerging Technology
%@ 0975-8887
%V ICAET2016
%N 9
%P 28-31
%D 2016
%I International Journal of Computer Applications
Abstract

In the modern era, as the circuit density is increasing thereby, its complexity is also increasing dramatically. Therefore it effect the processing speed, arithmetic and logical operations of the processor. Hence proposed design of the 8 bits Vedic multiplier which simplify the arithmetical operations compares to conventional multiplier. Moreover, it takes the minimum access time to execute mathematical operation. The proposed multiplier is design by use of Ripple carry adder by using Wallace tree methods. The proposed design is coded in Verilog in Xilinx 14. 7 tool and analysis is done using RTL schematics. The proposed design takes less area and access time as compared to conventional multipliers because the number of gates is reduced to perform any operation compared to other multipliers. Moreover, proposed algorithm is simple and faster as compared to other multiplier.

References
  1. B. Ramkumar and H. M. Kittur, "Low-power and area-efficient carry select adder," IEEE Trans. Very Large Scale Integrated. (VLSI) Syst. , (20) 2, pp. 371–375 ( 2012).
  2. H. D. Tiwari, G. Gankhuyag, C. M. Kim, and Y. B. Cho, "Multiplier design based on ancient Indian Vedic mathematics", Proc. Int SoC Design Conf. , pp. 65-68. (2008).
  3. R. K. Krishnamurthy "A low power 16 bit Accumulator using series- regulated Mixed Swing Technique"IEEE (1998).
  4. S. Patil "Design of speed and power efficient multipliers using Vedic Mathematics with VLSI implementation" IEEE, (2014).
  5. P. Kumar "FPGA Implementation of high speed 8-bit Vedic Multiplier using barrel shifter" IEEE (2013).
  6. M. Poornima, Shivaraj Kumar Patil, Shivu Kumar , K P Shridhar, "Implementation of Multiplier using Vedic Algorithm", International Journal of Innovative Technology and Exploring Engineering (IJITEE), ISSN 2278-3075 ( 2) pp. 219-223( 2013).
  7. Leonard Gibson Moses S, Thilagar M, "VLSI Implementation of High Speed DSP algorithms using Vedic Mathematics", Singaporean Journal Scientific Research( 2) 1, pp. 138-140(2010).
  8. S. Palnitkar "Verilog HDL ( A Guide to a Digital design and synthesis )
  9. S. Kumaravel, Ramalatha Marimuthu, "VLSI Implementation of High Performance RSA Algorithm Using Vedic Mathematics," ICCIMA, (4) pp. 126-128, (2007).
Index Terms

Computer Science
Information Sciences

Keywords

Vedic Multiplier Urdhav Tribhayam Sutra Ripple Carry Adder