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An Optimized Circuit of 8:1 Multiplexer Circuit using Reversible Logic Gates

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IJCA Proceedings on International Conference on Communication, Computing and Information Technology
© 2015 by IJCA Journal
ICCCMIT 2014 - Number 3
Year of Publication: 2015
Authors:
O. P. Singh
Vandana Shukla
G. R. Mishra
R. K. Tiwari

O.p.singh, Vandana Shukla, G R Mishra and R K.tiwari. Article: An Optimized Circuit of 8:1 Multiplexer Circuit using Reversible Logic Gates. IJCA Proceedings on International Conference on Communication, Computing and Information Technology ICCCMIT 2014(3):17-20, March 2015. Full text available. BibTeX

@article{key:article,
	author = {O.p.singh and Vandana Shukla and G. R. Mishra and R. K.tiwari},
	title = {Article: An Optimized Circuit of 8:1 Multiplexer Circuit using Reversible Logic Gates},
	journal = {IJCA Proceedings on International Conference on Communication, Computing and Information Technology},
	year = {2015},
	volume = {ICCCMIT 2014},
	number = {3},
	pages = {17-20},
	month = {March},
	note = {Full text available}
}

Abstract

Designing of reversible circuit has become the promising area for researchers. The designing of digital circuits using reversible logic should have zero power loss in ideal conditions. However in practical aspect, it does not occur. This paper illustrates an optimized 8:1 multiplexer circuit grounded on reversible logic using a combination of available reversible logic gates. The multiplexer is optimized on the basis of two parameters namely total number of reversible gates used in the design of the circuits and total garbage outputs generated. This circuit is more advantageous for further designing of any digital circuit with low power loss. The devices designed through this circuit would have better performance as compared to the existing circuits.

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