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Reseach Article

Asynchronous Router for Network-on-Chip on FPGA

Published on September 2015 by Gauri Suresh Bhosale, Arati S. Phadke
CAE Proceedings on International Conference on Communication Technology
Foundation of Computer Science USA
ICCT2015 - Number 1
September 2015
Authors: Gauri Suresh Bhosale, Arati S. Phadke
c7db2338-a43e-40df-a1a8-f27d72558d1c

Gauri Suresh Bhosale, Arati S. Phadke . Asynchronous Router for Network-on-Chip on FPGA. CAE Proceedings on International Conference on Communication Technology. ICCT2015, 1 (September 2015), 1-5.

@article{
author = { Gauri Suresh Bhosale, Arati S. Phadke },
title = { Asynchronous Router for Network-on-Chip on FPGA },
journal = { CAE Proceedings on International Conference on Communication Technology },
issue_date = { September 2015 },
volume = { ICCT2015 },
number = { 1 },
month = { September },
year = { 2015 },
issn = 0975-8887,
pages = { 1-5 },
numpages = 5,
url = { /proceedings/icct2015/number1/22630-1530/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 CAE Proceedings on International Conference on Communication Technology
%A Gauri Suresh Bhosale
%A Arati S. Phadke
%T Asynchronous Router for Network-on-Chip on FPGA
%J CAE Proceedings on International Conference on Communication Technology
%@ 0975-8887
%V ICCT2015
%N 1
%P 1-5
%D 2015
%I International Journal of Computer Applications
Abstract

In Network-on-chip router is the main block where one of the major decisions about the route direction is taken. This paper presents asynchronous router implemented using handshaking signals. Distributed routing with 3X3 Mesh topology is used in this design. 2D Mesh is the most common topologies due to its grid-type shape and regular structure which is most appropriate for the two dimensional layout on a chip. The design is synthesized for the Stratix II EP2S15F484C3 FPGA using Quartus II software. The router supports maximum of five simultaneous routing requests.

References
  1. Hatem, F. O. , & Kumar, T. N. (2013, April). A low-area asynchronous router for clock-less network-on-chip on a FPGA. In Computers & Informatics (ISCI), 2013 IEEE Symposium on (pp. 152-158). IEEE.
  2. Asghari, S. A. , Pedram, H. , & Khademi, M. (2009, October). A flexible design of network on chip router based on handshaking communication mechanism. In Computer Conference, 2009. CSICC 2009. 14th International CSI (pp. 225-230). IEEE.
  3. Dally, W. J. , & Towles, B. (2001). Route packets, not wires: on-chip interconnection networks. In Design Automation Conference, 2001. Proceedings (pp. 684-689). IEEE.
  4. Pande, P. P. , Grecu, C. , Jones, M. , Ivanov, A. , & Saleh, R. (2005). Performance evaluation and design trade-offs for network-on-chip interconnect architectures. Computers, IEEE Transactions on, 54(8), 1025-1040.
  5. Lee, S. E. , & Bagherzadeh, N. (2006, October). Increasing the throughput of an adaptive router in network-on-chip (NoC). In Proceedings of the 4th international conference on Hardware/software codesign and system synthesis (pp. 82-87). ACM.
  6. Sonal S. Bhople, M. A. Gaikwad. A Comparative Study of Different Topologies for Network-On-Chip Architecture. International Journal of Computer Applications (0975 – 8887) "Recent Trends in Engineering Technology-2013" (pp. 27-29)
  7. Pande, P. P. , Grecu, C. , Jones, M. , Ivanov, A. , & Saleh, R. (2005). Performance evaluation and design trade-offs for network-on-chip interconnect architectures. Computers, IEEE Transactions on, 54(8), 1025-1040.
  8. Chawade, S. D. , Gaikwad, M. A. , & Patrikar, R. M. (2012). Review of XY Routing Algorithm for Network-On-Chip Architecture. International Journal of Computer Applications, 43(21).
  9. Zhang, W. , Wu, W. , Zuo, L. , & Peng, X. (2009, December). The buffer depth analysis of 2-Dimension mesh topology Network-on-Chip with Odd-Even routing algorithm. In Information Engineering and Computer Science, 2009. ICIECS 2009. International Conference on (pp. 1-4). IEEE.
  10. Glass, C. J. , & Ni, L. M. (1992, April). The turn model for adaptive routing. In ACM SIGARCH Computer Architecture News (Vol. 20, No. 2, pp. 278-287). ACM.
Index Terms

Computer Science
Information Sciences

Keywords

Network On Chip Wormhole Switching Xy Routing Algorithm Asynchronous Router