CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Simulation and Design of Two Full Adder Cells in Subthreshold Region by Various CMOS Technologies and Compare Together

Published on None 2011 by Manijeh Alizadeh, Behjat Forouzandeh, Reza Sabbaghi-nadooshan
journal_cover_thumbnail

International Conference on VLSI, Communication & Instrumentation
Foundation of Computer Science USA
ICVCI - Number 18
None 2011
Authors: Manijeh Alizadeh, Behjat Forouzandeh, Reza Sabbaghi-nadooshan
e4b0bb34-aacf-49b3-a006-44dfbda650e2

Manijeh Alizadeh, Behjat Forouzandeh, Reza Sabbaghi-nadooshan . Simulation and Design of Two Full Adder Cells in Subthreshold Region by Various CMOS Technologies and Compare Together. International Conference on VLSI, Communication & Instrumentation. ICVCI, 18 (None 2011), 6-11.

@article{
author = { Manijeh Alizadeh, Behjat Forouzandeh, Reza Sabbaghi-nadooshan },
title = { Simulation and Design of Two Full Adder Cells in Subthreshold Region by Various CMOS Technologies and Compare Together },
journal = { International Conference on VLSI, Communication & Instrumentation },
issue_date = { None 2011 },
volume = { ICVCI },
number = { 18 },
month = { None },
year = { 2011 },
issn = 0975-8887,
pages = { 6-11 },
numpages = 6,
url = { /proceedings/icvci/number18/2763-1662/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on VLSI, Communication & Instrumentation
%A Manijeh Alizadeh
%A Behjat Forouzandeh
%A Reza Sabbaghi-nadooshan
%T Simulation and Design of Two Full Adder Cells in Subthreshold Region by Various CMOS Technologies and Compare Together
%J International Conference on VLSI, Communication & Instrumentation
%@ 0975-8887
%V ICVCI
%N 18
%P 6-11
%D 2011
%I International Journal of Computer Applications
Abstract

This paper presents two new 1-bit full adder cells operating in subthreshold region with 65nm, 90nm and 0.18um technologies. Circuits designed in this region usually consume less power. Inverse Majority Gate (IMG) together with NAND/NOR were used as the main computational building blocks. A modification was done to optimize W/L ratios with different supply voltages. We used W/L ratios for all the PMOS transistors 1.5 times the ratio of W/L for all NMOS transistors. Compared with a previously reported minority-3 based full adder; the results involve better performance in terms of power, delay, and PDP.

References
  1. Aunet, S., Oelmann, B., Abdalla, S. and Berg, Y. 2004. “Reconfigurable Sub-threshold CMOS Perceptron,” International Joint Conference on Neural Networks, IJCNN, pp. 1983-1988.
  2. Aunet, S. 2007. Kretselement U.S. Patent 7,288,968.
  3. Granhaug, K. and Aunet, S. 2006. “Six Subthreshold Full Adder Cells characterized in 90 nm CMOS technology,” DDECS, pp. 27-32.
  4. Aunet, S. and Beiu, V. 2005. “Ultra low power fault tolerant neural inspired CMOS logic,” in Proc. IEEE Int. Joint Conf. Neural Network, pp. 2843-2848.
  5. Aunet, S. 2003. Kretselement, Norwegian patent application, no. 20035537, Leiv Eiriksson Nyskapning, Trondheim, Norway.
  6. Moalemi, V. and Afzali-Kusha, A. 2007. “Sub Threshold 1 Bit Full Adder Cells in Sub100 nm Technology,” IEEE Computer Society Annual Symposium on VLSI, pp. 514- 515.
  7. Soeleman, H., Roy, K. and. Paul,B.C. 2001. “Robust subthreshold logic for ultra-low power operation,” IEEE Trans. VLSI Syst.
  8. Aunet, S., Oelmann, B.,Andreas,P. and Berg Y. 2008. “Real- Time Reconfigurable Subthreshold CMOS Perceptron,”IEEE Transaction 0n Neural Network, Vol.19, No.4, pp. 645-657, APRIL 2008.
  9. Razavi, B. Design of Analog CMOS Integrated Circuits.
  10. Navi, K., Moaiyeri, M.H., Faghih Mirzaee, R., Hashemipour, O. and Mazloom Nezhad, B. 2009. “Two novel lowpower full adders based on majority-not gates”, Elsevier, Microele-ctronics Journal Journal, Vol. 40, Issue. 1, pp. 126- 130.
  11. Shams, A.M. and Bayoumi, M.A. 2000. “A Novel High- Performance CMOS 1-bit Full Adder Cell,”IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, Vol. 47, No. 5, pp. 478-481, May 2000.
  12. Shams, A.M., Darwish, T.K. and Bayoumi, M.A. 2002. “Perfor- mance Analysis of Low-Power 1-Bit CMOS Full Adder Cells,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 1, pp. 20-29, Feb. 2002.
Index Terms

Computer Science
Information Sciences

Keywords

VLSI Subthreshold full adder inverse majority gate