The week's pick
Reseach Article
Hetero Double Gate-dielectric Tunnel FET with record high ION/ IOFF ratio
| International Conference on VLSI, Communication & Instrumentation |
| Foundation of Computer Science USA |
| ICVCI - Number 4 |
| None 2011 |
| Authors: Brinda Bhowmick, S. Baishya |
| 15880e92-63d9-45f2-b9d9-9138b9ef1d13 |
Brinda Bhowmick, S. Baishya . Hetero Double Gate-dielectric Tunnel FET with record high ION/ IOFF ratio. International Conference on VLSI, Communication & Instrumentation. ICVCI, 4 (None 2011), 11-13.
Abstract
To manage the increasing static leakage in low power applications and reduced Ion/Ioff due to aggressive scaling of MOS transistors, Tunnel FET (TFET) devices are considered as the most promising candidates because of their excellent immunity against such important short channel effects. Solutions for leakage reduction as well as improving on current of the device are sought at the device design and process technology levels. In this paper, we propose a novel design for a hetero double gate dielectric tunnel field effect transistor (HDG-TFET). Simulation of this device characteristics show significant improvement over conventional double gate devices with high K only gate dielectric TFET. In this device, a low K gate oxide is used at the drain end and a high K gate oxide is used at the source end with low band gap material in source region. Ambipolar behavior at the drain end can be suppressed and a record high Ion/Ioff of the order of 10 13 is achieved.
References
- M.R. William and A.J.A Gehan, “ Silicon surface tunnel transistor,” Appl. Phys. Lett.,vol 67,no.4,pp.494-496, Jul. 1995.
- K Boucart and A.M.Ionescu, “Double-gate tunnel FET with high-k gate Dielectric.” IEEE Trans. Electron Devices, vol.54,no.7,pp.1725-1733,Jul.2007.
- J.AppenzellerY.M.Lin, J.Knoch. and P.Avouris,” Band to band tunneling in carbon Nanotube field-effect transistors,” Phys.RevLett. Vol.93.no19.196805-1-196805-4. Nov.2004.
- C.Aydin,etal.,”Lateral interband tunneling transistor in silicon-on-insulator, “ Appl.Phys.Lett., vol.84, no.10, 2004, pp.1780-1782.
- K.Kim and J.Fossum” Double-Gate CMOS: Symmtrical- Versus Asymmetrical-GateDevices,” IEEE TransElec.Dev., vol.48, no.2,2001,pp.294-299.
- F.BalestraS.Cristoloveanu, M.Benachir, J.Brini and T.elewa,” Double-gate silicon-on-insulator transistor with volume inversion A newly device with greatly enhanced performance, IEEE Elec.Dev. Lett.,vol.8,no.9,1987,pp.410-412.
- ITRS Roadmap,2005,available online at http://www.itrs.net
- K. Bhuwalka, J. Schulze, and I.Eisele, A Simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET, IEEE Trans.Elec.Dev., vol.52, no.7,2005,pp 1541-1547.
- S.V.Anne, G.V. William. M.Karen, and G Guido, “ TFET without gate-drain overlap,” Appl.Phys.Lett” vol.91, no.5, p.053102, 2007.
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