The week's pick
Reseach Article
On the Design of High-Performance CMOS 1-Bit Full Adder Circuits
| International Conference on VLSI, Communication & Instrumentation |
| Foundation of Computer Science USA |
| ICVCI - Number 5 |
| None 2011 |
| Authors: Shivshankar Mishra, V. Narendar, Dr. R. A. Mishra |
| e9115bbb-9962-4228-9f5a-b462e01d95a7 |
Shivshankar Mishra, V. Narendar, Dr. R. A. Mishra . On the Design of High-Performance CMOS 1-Bit Full Adder Circuits. International Conference on VLSI, Communication & Instrumentation. ICVCI, 5 (None 2011), 35-38.
Abstract
In this paper, two high performance full adder circuits are proposed. We simulated these two full adder circuits using Cadence VIRTUOSO environment in 0.18 μm UMC CMOS technology and compared the Power dissipation, time delay, and power delay product (PDP) of the proposed circuits with other 10 transistor full adders. Simulation results show that for the supply voltage of 1.8V, these circuits are suitable for arithmetic circuits and other VLSI applications with very low power consumption and very high speed performance.
References
- Rabaey J. M., A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, A Design Perspective, 2nd 2002, Prentice Hall, Englewood Cliffs, NJ.
- Uyemura J., CMOS Logic Circuit Design, Kluwer, 1999, ISBN 0-7923-8452-0.
- N. Weste, K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, Addison-Wesley, 1993.
- Dan Wang, Maofeng Yang, Wu Cheng, Xuguang Guan, Zhangming Zhu, Yintang Yang, ”Novel Low Power Full Adder Cells in 180nm CMOS Technology”, 4th IEEE Conference on Industrial Electronics and Applications, ICIEA 2009, pp 430-433.
- Y. Jiang, A. A. Sheraidah, Y. Wang, E. Sha, and J. G. Chung, "A novel multiplexer-based low-power full adder," IEEE Trans. Circuits Syst. II. vol. 51, pp. 345-348, Jul. 2004.
- Mahmoud, H.A.; Bayoumi, M.A, “A 10-transistor low-power high speed full adder cell”, IEEE International Symposium on Circuits and Systems, vol-1, pp. 43-46, 1999.
- Lu Junming; Shu Yan; Lin Zhenghui; Wang Ling,” A Novel 10-transistor Low-power High-speed Full adder cell”, Proceedings of 6th International Conference on Solid-State and Integrated-Circuit Technology, vol-2, pp. 1155-1158,2001.
- R. Zimmermann, W. Fichtner, Low-power logic styles:CMOS versus pass transistor logic, IEEE J. Solid-State Circuits, 32(7), pp. 1079-1090, 1997.
- K Yano, Y Sasaki, K Rikino and KSeki, Top-down pass transistor logic design, IEEE J. Solid- State Circuits, vol. - 31, pp. 792-803, 1996.
- Jin-Fa-Lin, Yin Tsung Hwang, Ming-Hwa Sheu, and Cheng-Che Ho, "A Novel High-Speed and Energy Efficient 10 Transistor Full Adder Design" IEEE Trans. Circuits Syst. I: Regular Papers, vol.54, no.5, pp.1050-1059, May 2007.
- A. Fayed and M. Bayoumi, "A low-power 10-transistor full adder cell for embedded architectures," in Proc. IEEE Symp. Circuits Syst., Sydney, Australia, May 2001, pp. 226–229.
- H. T. Bui, Y. Wang, and Y. Jiang, "Design and analysis of low-power 10-transistor full adders using XOR-XNOR gates," IEEE Trans. Circuits Syst. II, Analog Digit Signal Process., vol. 49, no. 1, pp. 25–30, Jan. 2002.
- Adarsh Kumar Agrawal, Shivshankar Mishra, and R. K. Nagaria, “Proposing a Novel Low-Power High-Speed Mixed GDI Full Adder Topology”, accepted in Proceeding of IEEE International Conference on Power, Control and Embedded System (ICPCES), 28 Nov.-1Dec. 2010.
- N. M. Chore, and R. N. Mandavgane, “A Survey of Low Power High Speed 1 Bit Full Adder”, Proceeding of the 12th International Conference on Networking, VLSI and Signal Processing, pp. 302-307,2010.
Index Terms
Keywords