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Reseach Article

Efficient Hardware Reduction of FIR Filter for Parallel Data in Mixed Signal Processing

Published on March 2012 by Jayavrinda Vrindavanam, Resel Parameswaran
International Conference and Workshop on Emerging Trends in Technology
Foundation of Computer Science USA
ICWET2012 - Number 1
March 2012
Authors: Jayavrinda Vrindavanam, Resel Parameswaran
da597a76-f8a7-45f8-9a88-0282a90345f9

Jayavrinda Vrindavanam, Resel Parameswaran . Efficient Hardware Reduction of FIR Filter for Parallel Data in Mixed Signal Processing. International Conference and Workshop on Emerging Trends in Technology. ICWET2012, 1 (March 2012), 18-23.

@article{
author = { Jayavrinda Vrindavanam, Resel Parameswaran },
title = { Efficient Hardware Reduction of FIR Filter for Parallel Data in Mixed Signal Processing },
journal = { International Conference and Workshop on Emerging Trends in Technology },
issue_date = { March 2012 },
volume = { ICWET2012 },
number = { 1 },
month = { March },
year = { 2012 },
issn = 0975-8887,
pages = { 18-23 },
numpages = 6,
url = { /proceedings/icwet2012/number1/5314-1005/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference and Workshop on Emerging Trends in Technology
%A Jayavrinda Vrindavanam
%A Resel Parameswaran
%T Efficient Hardware Reduction of FIR Filter for Parallel Data in Mixed Signal Processing
%J International Conference and Workshop on Emerging Trends in Technology
%@ 0975-8887
%V ICWET2012
%N 1
%P 18-23
%D 2012
%I International Journal of Computer Applications
Abstract

The paper presents a novel method of structure for designing and implementation of hardware reduced FIR filter in mixed signal processing domain for parallel data processing. Supported by a review of the literature, the paper demonstrates that the proposed methodology is superior, economical and can be applied in to applications like bio-medical and audio signals. The results show improved performance and cost reduction, which has practical implications in terms of applications.

References
  1. Resel,P., Jayavrinda, V., 2011; Efficient hardware reduction of FIR Filter in mixed signal processing; proceedings of IEEE International Conference on Intelligent Computing and Intelligent Systems (ICIS 2011),IEEE Xplore, China.
  2. Vinod, A.P., Lai, E.M.-K., Premkuntar, A.B., Lau, C.T. 2003. FIR filter implementation by efficient sharing of horizontal and vertical common subexpressions; Electronics Letters , Issue NO. 2, pages 251-253.
  3. Shahramian, S., Carusone, T.C. 2004. Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization; , Proceedings of the 2004 International Symposium on Circuits and Systems.
  4. Chao Cheng; Parhi, K.K.; 2004, Hardware efficient fast parallel FIR filter structures based on iterated short convolution, IEEE Transactions on Circuits and Systems I, Issue No 8, pages 1492-1500,
  5. Chao Cheng., Parhi, K.K. 2005. Further complexity reduction of parallel FIR filters; ISCAS IEEE International Symposium on Circuits and Systems.
  6. Chao Cheng Parhi, K.K. 2007, Low- Cost Parallel FIR Filter Structures With 2-Stage Parallelism, IEEE Transactions on Circuits and Systems, February, Pages 280-290.
  7. Hai Huyen Dam, Sven Nordholm and Antonio Cantoni 2005; Uniform FIR filterbank Optimisation with Group Delay Specifications, IEEE Transactions on Signal Processing, Vol. 53, No 11, November.
  8. Dusan M. Kodek, 2005. Performance Limit of Finite Wordlength FIR Digital Filters, IEEE Transactions on Signal Processing, Vol. 53, No 7, July.
  9. Mehboob, R.; Khan, S.A.; Qamar, R’ 2009; FIR filter design methodology for hardware optimised implementation, IEEE Transactions on Consumer Electronics, Issue NO. 3, IEEE Consumer Electronics Society, August.
  10. Tayab D. Memon, Paul Beckett, Amin Z. Sadik 2009, "Performance-Area Tradeoffs in the Design of a Short Word Length FIR Filter," MEMS, NANO, and Smart Systems.
  11. Tsao, Yu-chi, Choi, Ken, 2011, Hardware-efficient parallel FIR digital filter structures for symmetric convolutions, IEEE International Symposium on Circuits and Systems, May, Rio de Janeiro, Brazil, pages 2301-2304.
  12. P. Gentili, F. Piazza, A. Uncini 1995; Efficient genetic algorithm design for power-of-two FIR filters, IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol 2.
  13. Fifth International Conference on MEMS, NANO, and Smart Systems, 2009; Fifth International Conference on MEMS NANO, and Smart Systems; pages. 67-71.
Index Terms

Computer Science
Information Sciences

Keywords

Mixed Domain Hardware FIR Multipliers adders integrator summing integrator scaling resistors decimation algorithm stopband and sinusoidal wave.