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An Approach for Minimizing CMOS Layout by Applying Euler�s Path Rule

Published on March 2012 by R.H.Khade, D.S. Chaudhari
International Conference and Workshop on Emerging Trends in Technology
Foundation of Computer Science USA
ICWET2012 - Number 10
March 2012
Authors: R.H.Khade, D.S. Chaudhari
6cfd8d96-342c-4282-a611-647223017cf7

R.H.Khade, D.S. Chaudhari . An Approach for Minimizing CMOS Layout by Applying Euler�s Path Rule. International Conference and Workshop on Emerging Trends in Technology. ICWET2012, 10 (March 2012), 18-21.

@article{
author = { R.H.Khade, D.S. Chaudhari },
title = { An Approach for Minimizing CMOS Layout by Applying Euler�s Path Rule },
journal = { International Conference and Workshop on Emerging Trends in Technology },
issue_date = { March 2012 },
volume = { ICWET2012 },
number = { 10 },
month = { March },
year = { 2012 },
issn = 0975-8887,
pages = { 18-21 },
numpages = 4,
url = { /proceedings/icwet2012/number10/5385-1076/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference and Workshop on Emerging Trends in Technology
%A R.H.Khade
%A D.S. Chaudhari
%T An Approach for Minimizing CMOS Layout by Applying Euler�s Path Rule
%J International Conference and Workshop on Emerging Trends in Technology
%@ 0975-8887
%V ICWET2012
%N 10
%P 18-21
%D 2012
%I International Journal of Computer Applications
Abstract

An attempt has been made to reduce area requirement while improving electrical characteristics during very large scale integration (VLSI) design. The area can be reduced by designing a layout without diffusion breaks. In this paper, a method is proposed that provides more compact layout without breaks in diffusion with minimal metal pattern, less contacts and low parasitic capacitance. A novel approach towards constructing Euler’s path on complementary metal oxide semiconductor (CMOS) circuit is also discussed

References
  1. Shun-wen Cheng, Kou-Hsing Cneng. 2004. “Modified Euler path Rule for MOS Layout Minimization. ”, in IEEE Asia-Pacific Conference on Circuits and Systems, pp, 541-544, December 6-9, 2004
  2. Shaoan Yan, Dongen Li, Liming Wang, Yongguang Xiao, Minghua Tang. “A Novel Methodology of Layout Design by applying Euler path”, .10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT),2010
  3. Y.J. Kwon and C.M. Kyung, “An Algorithm for optimal layouts of CMOS complex logic Modules“, in Proc. IEEE International Symposium on Circuits and Systems, vol.5, pp. 3126-3129, June 1991.
  4. T. Nakagaki, S. Yamada and K.Fukunaga, “ Fast Optimal Algorithm for the CMOS Functional Cell Layout Based on Transistor Reordering,” in Proc. IEEE International Symposium Circuits and System, vol.5, pp, 2116-2119, May 1992.
  5. N.H.E. Weste , K. Eshraghian, Principle of CMOS VLSI Design. 2nd Edition, Reading : Addison-wesley, 1993.
  6. John P. Uyemura, Introduction to VLSI circuits and Systems, John Wiley & Sons, p.80,2002..
  7. Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, Analysis and Design, 3rd Edition, Tata McGraw- Hill Edition, 2003.
Index Terms

Computer Science
Information Sciences

Keywords

Euler’s path Optimal layout Metal pattern Diffusion breaks