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Reseach Article

Channelization and Frequency Tuning using FPGA for UMTS Baseband Application

Published on March 2012 by Mahesh M.Gadag, S. Ganesh Naik, Vinayak Miskin, Dundesh S. K
International Conference and Workshop on Emerging Trends in Technology
Foundation of Computer Science USA
ICWET2012 - Number 6
March 2012
Authors: Mahesh M.Gadag, S. Ganesh Naik, Vinayak Miskin, Dundesh S. K
07a56154-fa4d-405c-b22f-3d66f240201e

Mahesh M.Gadag, S. Ganesh Naik, Vinayak Miskin, Dundesh S. K . Channelization and Frequency Tuning using FPGA for UMTS Baseband Application. International Conference and Workshop on Emerging Trends in Technology. ICWET2012, 6 (March 2012), 6-10.

@article{
author = { Mahesh M.Gadag, S. Ganesh Naik, Vinayak Miskin, Dundesh S. K },
title = { Channelization and Frequency Tuning using FPGA for UMTS Baseband Application },
journal = { International Conference and Workshop on Emerging Trends in Technology },
issue_date = { March 2012 },
volume = { ICWET2012 },
number = { 6 },
month = { March },
year = { 2012 },
issn = 0975-8887,
pages = { 6-10 },
numpages = 5,
url = { /proceedings/icwet2012/number6/5351-1042/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference and Workshop on Emerging Trends in Technology
%A Mahesh M.Gadag
%A S. Ganesh Naik
%A Vinayak Miskin
%A Dundesh S. K
%T Channelization and Frequency Tuning using FPGA for UMTS Baseband Application
%J International Conference and Workshop on Emerging Trends in Technology
%@ 0975-8887
%V ICWET2012
%N 6
%P 6-10
%D 2012
%I International Journal of Computer Applications
Abstract

Wireless base station transceiver front- end signal processing often is performed using digital techniques. As bandwidths and IF digital-analog sampling frequencies increase, a large number of calculations are required for channelization, frequency tuning, and rate conversion. As new standards emerge, the design options are numerous for multi-protocol and multichannel transceiver front ends. The inherent flexibility of Xilinx FPGAs along with recent advances in their architectures makes them ideal for cost-efficient implementations of digital transceiver front-end functions, such as down conversions and precise channel filtering. The Xilinx development environment for digital signal processing (DSP) functions provides all of the resources needed for simultaneously developing signal processing algorithm and circuit parameters. This paper describes a design using some IP cores of Xilinx system generator and simulink software in designing the single channel to multichannel digital down converters (DDCs) for UMTS base stations. The four- channel implementations are described that efficiently map the DSP algorithms into the resources of the Virtex®-5 families of FPGAs.

References
  1. "Physical Layer Standard for cdma2000 Spread Spectrum Systems", Revision D, 3GPP2 C.S0002-D, version 1.0, February13, 2004
  2. D. Babic, J. Vesma, and M. Renfors, “Decimation by irrational factor using CIC filter and linear interpolation,” IEEE International Conference on Acoustics, Speech, Signal Processing, May 2001.
  3. E. B. Hogenauer “An Economical Class of Digital Filters for Decimation and Interpolation”, IEEE Trans. Acoust., Speech Signal Processing, Vol 29, No 2, pp 155-162, April1981.
  4. P.P. Vaidyanathan, “Multirate Systems and Filter Banks”, Prentice Hall, Englewood Cliffs, New Jersey, 1993.
  5. Mohamed Al Mahdi Eshtawie, and Masuri Bin “OthmanAn Algorithm Proposed for FIR Filter Coefficients Representation” World Academy of Science, Engineering and Technology
  6. Direct digital synthesizers (DDS), Xilinx logi core generation April 28, 2005.
  7. Xilinx logi core MAC FIR v5.1 April 28, 2005 Product specification.
Index Terms

Computer Science
Information Sciences

Keywords

IF FPGA DSP DDC CDMA UMTS