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Design of RS Code Using Simulink Platform

IJCA Proceedings on International Conference and workshop on Emerging Trends in Technology (ICWET 2012)
© 2012 by IJCA Journal
icwet2012 - Number 8
Year of Publication: 2012
B. K. Mishra
Sukruti Kaulgud
Sandhya Save

B K Mishra, Sukruti Kaulgud and Sandhya Save. Article: Design ofRS Code Using Simulink Platform. IJCA Proceedings on International Conference and workshop on Emerging Trends in Technology (ICWET 2012) icwet(8):1-5, March 2012. Full text available. BibTeX

	author = {B. K. Mishra and Sukruti Kaulgud and Sandhya Save},
	title = {Article: Design ofRS Code Using Simulink Platform},
	journal = {IJCA Proceedings on International Conference and workshop on Emerging Trends in Technology (ICWET 2012)},
	year = {2012},
	volume = {icwet},
	number = {8},
	pages = {1-5},
	month = {March},
	note = {Full text available}


Reed–Solomon (RS) codes are non-binary cyclic error correcting codes widely used for robust and energy efficient transmissions. They are block-based error correcting codes with a wide range of applications in digital communications like digital audio and vidco, magnetic and optical recording,computcr memory, cable modem. xDSLwireless andsatellite connnunications systems etc. In this work, we proposed Simulink based modelfor performance analysis of the RS (n,k) code architecture and implement the same on FPGA.The experimental results of RS encoder simulationconfirm that this model isfast and parameterizable. The biggest advantage of this method, it can be implemented on FPGAwith less amount of logic blocks saving area and time. This feature makes it an attractive method for SoC application


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