Reed–Solomon (RS) codes are non-binary cyclic error correcting codes widely used for robust and energy efficient transmissions. They are block-based error correcting codes with a wide range of applications in digital communications like digital audio and vidco, magnetic and optical recording,computcr memory, cable modem. xDSLwireless andsatellite connnunications systems etc. In this work, we proposed Simulink based modelfor performance analysis of the RS (n,k) code architecture and implement the same on FPGA.The experimental results of RS encoder simulationconfirm that this model isfast and parameterizable. The biggest advantage of this method, it can be implemented on FPGAwith less amount of logic blocks saving area and time. This feature makes it an attractive method for SoC application

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Reed Solomon codes FPGA Matlab Simulink SoC error correcting codes