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Hardware Simulation of BPSK Modem

Published on April 2013 by Bhosle S. S., S. A. Shirsat, A. D. Jadhav
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International Conference and Workshop on Emerging Trends in Technology 2013
Foundation of Computer Science USA
ICWET2013 - Number 2
April 2013
Authors: Bhosle S. S., S. A. Shirsat, A. D. Jadhav
e202202e-6546-4152-acfd-4ef9472f011c

Bhosle S. S., S. A. Shirsat, A. D. Jadhav . Hardware Simulation of BPSK Modem. International Conference and Workshop on Emerging Trends in Technology 2013. ICWET2013, 2 (April 2013), 15-20.

@article{
author = { Bhosle S. S., S. A. Shirsat, A. D. Jadhav },
title = { Hardware Simulation of BPSK Modem },
journal = { International Conference and Workshop on Emerging Trends in Technology 2013 },
issue_date = { April 2013 },
volume = { ICWET2013 },
number = { 2 },
month = { April },
year = { 2013 },
issn = 0975-8887,
pages = { 15-20 },
numpages = 6,
url = { /proceedings/icwet2013/number2/11336-1352/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference and Workshop on Emerging Trends in Technology 2013
%A Bhosle S. S.
%A S. A. Shirsat
%A A. D. Jadhav
%T Hardware Simulation of BPSK Modem
%J International Conference and Workshop on Emerging Trends in Technology 2013
%@ 0975-8887
%V ICWET2013
%N 2
%P 15-20
%D 2013
%I International Journal of Computer Applications
Abstract

This paper presents the hardware simulation of a BPSK Modulator and Demodulator using Matlab/Simulink environment and System Generator, a tool from Xilinx used for FPGA design of the Modulator and Demodulator. VHDL programming code is used to generate BPSK digital signal. The modulator and demodulator VHDL algorithm has been simulated in MATLAB R2009a and system generators Xilinx ISE 12. 1. This paper also focuses on error performance parameter of BPSK modulation and demodulation schemes in AWGN channel.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Programmable Array Logic) Awgn (additive White Gaussian Noise) Ber (bit Error Rate) System Generator Xilinx Wavescope Resource Estimator Rrc (root Raised Cosine)