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A Low Jitter Phase Locked Loop for High Speed Serial Interfaces

Published on October 2014 by D Pavan Kumar Sharma, P Sreehari Rao
journal_cover_thumbnail

International Conference on Microelectronics, Circuits and Systems
Foundation of Computer Science USA
MICRO - Number 3
October 2014
Authors: D Pavan Kumar Sharma, P Sreehari Rao
68f32945-e8c4-4b0b-99ef-bf8fb19196a5

D Pavan Kumar Sharma, P Sreehari Rao . A Low Jitter Phase Locked Loop for High Speed Serial Interfaces. International Conference on Microelectronics, Circuits and Systems. MICRO, 3 (October 2014), 1-4.

@article{
author = { D Pavan Kumar Sharma, P Sreehari Rao },
title = { A Low Jitter Phase Locked Loop for High Speed Serial Interfaces },
journal = { International Conference on Microelectronics, Circuits and Systems },
issue_date = { October 2014 },
volume = { MICRO },
number = { 3 },
month = { October },
year = { 2014 },
issn = 0975-8887,
pages = { 1-4 },
numpages = 4,
url = { /proceedings/micro/number3/18322-1820/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Microelectronics, Circuits and Systems
%A D Pavan Kumar Sharma
%A P Sreehari Rao
%T A Low Jitter Phase Locked Loop for High Speed Serial Interfaces
%J International Conference on Microelectronics, Circuits and Systems
%@ 0975-8887
%V MICRO
%N 3
%P 1-4
%D 2014
%I International Journal of Computer Applications
Abstract

This paper presents a new circuit for clock generation. A new phase frequency detector is designed in 130nm CMOS process technology. The phase locked loop is designed to meet the 10BaseKR wire line communication standards. All the circuits are designed in current mode logic for high speed operation. The designed circuit dissipates mW. The voltage controlled oscillator has phase noise of -182. 2dBc/Hz at 1 MHz offset from center frequency. The designed phase locked loop has rms phase jitter of 44. 17fs.

References
  1. McNeill, J. A. , "Jitter in ring oscillators," Solid-State Circuits, IEEE Journal of , vol. 32, no. 6, pp. 870,879, Jun 1997.
  2. Hajimiri, A. ; Limotyrakis, S. ; Lee, T. H. , "Jitter and phase noise in ring oscillators," Solid-State Circuits, IEEE Journal of , vol. 34, no. 6, pp. 790,804, Jun 1999.
  3. Herzel, F. ; Razavi, B. , "A study of oscillator jitter due to supply and substrate noise," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol. 46, no. 1, pp. 56,62, Jan 1999.
  4. Razavi, B. , "A study of phase noise in CMOS oscillators," Solid-State Circuits, IEEE Journal of , vol. 31, no. 3, pp. 331,343, Mar 1996
  5. CMOS Circuit Design ,Layout and Sumulations by R. Jacob Baker,Wiley,2010.
  6. Design of Analog CMOS Integrated Circuits by Bahzad Razavi,TATA McGRAW-HILL ,2002.
  7. Qiyang Wu; Quach, T. K. ; Mattamana, A. ; Elabd, S. ; Orlando, P. L. ; Dooley, S. R. ; McCue, J. J. ; Creech, G. L. ; Khalil, W. , "Frequency Tuning Range Extension in LC-VCOs Using Negative-Capacitance Circuits," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol. 60, no. 4, pp. 182,186, April 2013.
  8. Changhua Cao; O, K. K. , "Millimeter-wave voltage-controlled oscillators in 0. 13-?m CMOS technology," Solid-State Circuits, IEEE Journal of , vol. 41, no. 6, pp. 1297,1304, June 2006.
  9. Fong, N. ; Jonghae Kim; Plouchart, J. -O. ; Zamdmer, N. ; Duixian Liu; Wagner, L. ; Plett, C. ; Tarr, G. , "A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology," Solid-State Circuits, IEEE Journal of , vol. 39, no. 5, pp. 841,846, May 2004 .
Index Terms

Computer Science
Information Sciences

Keywords

Wire Line Communication Phase Locked Loop Phase Noise Current Mode Logic.