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A Novel n-bit Arithmetic Logic Unit Design based on Reversible Logic

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IJCA Proceedings on National Symposium on Modern Information and Communication Technologies for Digital India
© 2016 by IJCA Journal
MICTDI 2016 - Number 1
Year of Publication: 2016
Authors:
Virender Singh
Ruchi Gupta

Virender Singh and Ruchi Gupta. Article: A Novel n-bit Arithmetic Logic Unit Design based on Reversible Logic. IJCA Proceedings on National Symposium on Modern Information and Communication Technologies for Digital India MICTDI 2016(1):27-30, December 2016. Full text available. BibTeX

@article{key:article,
	author = {Virender Singh and Ruchi Gupta},
	title = {Article: A Novel n-bit Arithmetic Logic Unit Design based on Reversible Logic},
	journal = {IJCA Proceedings on National Symposium on Modern Information and Communication Technologies for Digital India},
	year = {2016},
	volume = {MICTDI 2016},
	number = {1},
	pages = {27-30},
	month = {December},
	note = {Full text available}
}

Abstract

In this paper, the design of an N-bit reversible Arithmetic Logic Unit (ALU) is presented. In modern Era of circuit designing, complexity of circuit increases day by day. Hence power dissipation plays important role in designing of any digital circuit. There are two types of power losses, leakage power and dynamic. Reversible logic design can also be used for same objective reversible gates are used which have equal number of inputs and outputs. This research has focused on reducing dynamic power dissipation by reversible logic design which provides substantial reduction in dynamic power dissipation (~50% reduction is observed). The later design is found advantageous over the former irreversible designs in terms of power dissipation.

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