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Carry Speculative Adder with Variable Latency for Low Power VLSI

Published on September 2016 by Subhashinee A., Rajasekaran C.
National Conference on lnnovation in Computing and Communication Technology
Foundation of Computer Science USA
NCICCT2016 - Number 1
September 2016
Authors: Subhashinee A., Rajasekaran C.
552aefbc-81c2-490a-b736-30f5546148dd

Subhashinee A., Rajasekaran C. . Carry Speculative Adder with Variable Latency for Low Power VLSI. National Conference on lnnovation in Computing and Communication Technology. NCICCT2016, 1 (September 2016), 16-18.

@article{
author = { Subhashinee A., Rajasekaran C. },
title = { Carry Speculative Adder with Variable Latency for Low Power VLSI },
journal = { National Conference on lnnovation in Computing and Communication Technology },
issue_date = { September 2016 },
volume = { NCICCT2016 },
number = { 1 },
month = { September },
year = { 2016 },
issn = 0975-8887,
pages = { 16-18 },
numpages = 3,
url = { /proceedings/ncicct2016/number1/25864-2031/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on lnnovation in Computing and Communication Technology
%A Subhashinee A.
%A Rajasekaran C.
%T Carry Speculative Adder with Variable Latency for Low Power VLSI
%J National Conference on lnnovation in Computing and Communication Technology
%@ 0975-8887
%V NCICCT2016
%N 1
%P 16-18
%D 2016
%I International Journal of Computer Applications
Abstract

Arithmetic logic units and digital signal processors widely uses adders. It is the most complicated arithmetic circuits in digital electronics. The existing adders suffer from critical path delay, area overhead and power consumption. Speculative adders are designed with variable latency that combines speculation technique along with correction methodology to attain high performance in terms of low area overhead over the existing adders. In speculative adders the sum and carry generation part is separated to reduce the area overhead. Carry Speculative Adder (CSPA) uses carry predictor circuit to reduce power consumption and to reduce the computational time and it uses error recognition and error correction circuit to detect the fault occurred in the partial sum generator and to recover it to get accurate results. CSPA circuit provides error free output so that it can be used in many digital applications. This speculative adder can reduce the delay upto 11. 88 %.

References
  1. D. Mohapatra, A. Raghunathan, V. Gupta and K. Roy, "Low-power digital signal processing using approximate adders," IEEE Transaction Computer- Aided Design Integration Circuits Systems. , vol. 32, no. 1, pp. 124–137, Jan. 2013.
  2. N. Zhu, K. S. Yeo, W. L. Goh, and Z. H. Kong, "Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing," IEEE Transaction Very Large Scale Integration (VLSI) Syst. , vol. 18, no. 8, pp. 1225–1229, Aug. 2010.
  3. P. Varman, K. Du and K. Mohanram, "High performance reliable variable latency carry select addition," in Proceedings, Design Automation Test Conference Exhibition (DATE), Mar. 2012, pp. 1257–1262.
  4. Y. Chen et al. , "Variable-latency adder (VL-adder) designs for low power and NBTI tolerance," IEEE Transaction Very Large Scale Integration (VLSI) System, vol. 18, no. 11, pp. 1621–1624, Nov. 2010.
  5. Y. -H. Su, D. -C. Wang, S. -C. Chang, and M. -S. Malgorzata, "Performance optimization using variable-latency design style," IEEE Transaction Very Large Scale Integration (VLSI) Systems, vol. 19, no. 10, pp. 1874–1883, Oct. 2011.
  6. D. Baneres, J. Cortadella, and M. Kishinevsky, "Variable-latency design by function speculation," in Proceedings, Design Automation Test Conference Exhibition (DATE), Apr. 2009, pp. 1704–1709.
  7. D. Shin and S. K. Gupta, "Approximate logic synthesis for error tolerant applications," in Proceedings, Design Automation Test Conference Exhibition. (DATE), Mar. 2010, pp. 957–960.
  8. N. Zhu, W. L. Goh, and K. S. Yeo, "Ultra low-power high-speed flexible probabilistic adder for error-tolerant applications," in Proceedings Integration SoC Design Conference (ISOCC), Nov. 2011, pp. 393–396. K. Verma, P. Brisk, and P. Ienne, "Variable latency speculative addition: A new paradigm for arithmetic circuit design," in Proceedings, Design Automation Test Conference Exhibition (DATE), Mar. 2008, pp. 1250–1255. B. Kahng and S. Kang, "Accuracy-configurable adder for approximate arithmetic designs," in Proceedings, Design Automation Conference. (DAC), 2012, pp. 820–825.
  9. Y. Liu, Y. Sun, Y. Zhu, and H. Yang, "Design methodology of variable latency adders with multistage function speculation," in Proc. 11th International Symposium Qual Electron. Design (ISQED), Mar. 2010, pp. 824–830.
  10. M. Olivieri, "Design of synchronous and asynchronous variable-latency pipelined multipliers," IEEE Transaction Very Large Scale Integration (VLSI) Systems. , vol. 9, no. 2, pp. 365–376, Apr. 2001.
  11. Y. Chen, H. Li, J. Li, and C. -K. Koh, "Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI," in Proceedings Internationl. Symposium Low Power Electronic Design (ISLPED), Aug. 2007, pp. 195–200.
  12. Synopsys Design Compiler. (2010) [Online]. Available: http://www. synopsys. com.
Index Terms

Computer Science
Information Sciences

Keywords

Speculative Adder Variable Latency Error Detection Error Correction