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Design and Implementation of Energy Efficient Approximate Multiplier

IJCA Proceedings on National Conference on Information and Communication Technologies
© 2015 by IJCA Journal
NCICT 2015 - Number 1
Year of Publication: 2015
B. Anish Fathima
C. Vasanthanayaki

Anish B Fathima and C Vasanthanayaki. Article: Design and Implementation of Energy Efficient Approximate Multiplier. IJCA Proceedings on National Conference on Information and Communication Technologies NCICT 2015(1):19-23, September 2015. Full text available. BibTeX

	author = {B. Anish Fathima and C. Vasanthanayaki},
	title = {Article: Design and Implementation of Energy Efficient Approximate Multiplier},
	journal = {IJCA Proceedings on National Conference on Information and Communication Technologies},
	year = {2015},
	volume = {NCICT 2015},
	number = {1},
	pages = {19-23},
	month = {September},
	note = {Full text available}


Modern Digital signal processing and image processing applications are aiming towards energy efficiency. The prime arithmetic operation performed for these processes is multiplication. Hence energy efficiency of multiplication is critical. Since many digital applications use fixed- point arithmetic, it exhibits computational error tolerance. In this brief, a multiplier is proposed that can trade-off computational accuracy with energy consumption. Segmenting the original operands with significant bits and performing the multiplication only for those segments is the main principle. The proposed method of approximate multiplier consumes lesser power and hence notably lesser energy with average computational error of ~1%, when compared to the existing approximate multipliers with similar principle. Further optimization of the proposed multiplier is also done which improves the average computational accuracy along with a considerable reduction in the area consumed by the proposed multiplier.


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