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Performance Evaluation and Synthesis of Vedic Multiplier

IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012)
© 2012 by IJCA Journal
ncipet - Number 1
Year of Publication: 2012
Umesh Akare
T. V. More
R. S. Lonkar

Umesh Akare, T V More and R S Lonkar. Article: Performance Evaluation and Synthesis of Vedic Multiplier. IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012) ncipet(1):20-23, March 2012. Full text available. BibTeX

	author = {Umesh Akare and T. V. More and R. S. Lonkar},
	title = {Article: Performance Evaluation and Synthesis of Vedic Multiplier},
	journal = {IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012)},
	year = {2012},
	volume = {ncipet},
	number = {1},
	pages = {20-23},
	month = {March},
	note = {Full text available}


Digital multipliers are the core components of all the digital signal processors (DSPs) and the speed of the DSP is largely determined by the speed of its multipliers. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. Minimizing power consumption for digital systems involves optimization at all levels of the design. This optimization includes the implemented technology, the circuit style and topology, the architecture and at the highest level the algorithms that are being implemented. Multiplier is not only a high delay block but also a major source of power dissipation. This work presents a systematic design methodology for fast and area efficient digital multiplier based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics. The performance of this Vedic multiplier is compared with the conventional and fast multipliers being used in practice.


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