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Reseach Article

Performance Evaluation and Synthesis of Vedic Multiplier

Published on March 2012 by Umesh Akare, T. V. More, R. S. Lonkar
2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013)
Foundation of Computer Science USA
NCIPET - Number 1
March 2012
Authors: Umesh Akare, T. V. More, R. S. Lonkar
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Umesh Akare, T. V. More, R. S. Lonkar . Performance Evaluation and Synthesis of Vedic Multiplier. 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013). NCIPET, 1 (March 2012), 20-23.

@article{
author = { Umesh Akare, T. V. More, R. S. Lonkar },
title = { Performance Evaluation and Synthesis of Vedic Multiplier },
journal = { 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013) },
issue_date = { March 2012 },
volume = { NCIPET },
number = { 1 },
month = { March },
year = { 2012 },
issn = 0975-8887,
pages = { 20-23 },
numpages = 4,
url = { /proceedings/ncipet/number1/5193-1005/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013)
%A Umesh Akare
%A T. V. More
%A R. S. Lonkar
%T Performance Evaluation and Synthesis of Vedic Multiplier
%J 2nd National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2013)
%@ 0975-8887
%V NCIPET
%N 1
%P 20-23
%D 2012
%I International Journal of Computer Applications
Abstract

Digital multipliers are the core components of all the digital signal processors (DSPs) and the speed of the DSP is largely determined by the speed of its multipliers. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. Minimizing power consumption for digital systems involves optimization at all levels of the design. This optimization includes the implemented technology, the circuit style and topology, the architecture and at the highest level the algorithms that are being implemented. Multiplier is not only a high delay block but also a major source of power dissipation. This work presents a systematic design methodology for fast and area efficient digital multiplier based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics. The performance of this Vedic multiplier is compared with the conventional and fast multipliers being used in practice.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Digital Multiplier Optimization Urdhva Tiryakbhayam Vertical and crosswise algorithm bypassing algorithms