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A FPGA Implementation of a RISC Processor for Computer Architecture

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IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012)
© 2012 by IJCA Journal
ncipet - Number 1
Year of Publication: 2012
Authors:
Vijay R. Wadhankar
Vaishali Tehre

Vijay R Wadhankar and Vaishali Tehre. Article: A FPGA Implementation of a RISC Processor for Computer Architecture. IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012) ncipet(1):24-28, March 2012. Full text available. BibTeX

@article{key:article,
	author = {Vijay R. Wadhankar and Vaishali Tehre},
	title = {Article: A FPGA Implementation of a RISC Processor for Computer Architecture},
	journal = {IJCA Proceedings on National Conference on Innovative Paradigms in Engineering and Technology (NCIPET 2012)},
	year = {2012},
	volume = {ncipet},
	number = {1},
	pages = {24-28},
	month = {March},
	note = {Full text available}
}

Abstract

This paper is concerned with the design and implementation of a 32bit Reduced Instruction Set Computer (RISC) processor on a Field Programmable Gate Arrays (FPGAs). We are designing the processor with VHDL and the simulation using Altera Quartus Plus2, and we will implement on Altera cyclone II in FPGA.The test bench waveforms for the different parts of the processor are presented and the system architecture is demonstrated.

References

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Keywords