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Design and Implementation of Low Power and Highly Scaled DCT Architecture with CORDIC Algorithm

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IJCA Proceedings on National Conference on Power Systems and Industrial Automation
© 2015 by IJCA Journal
NCPSIA 2015 - Number 1
Year of Publication: 2015
Authors:
Bhaskar S. V.
Easwara M.

Bhaskar S.v. and Easwara M.. Article: Design and Implementation of Low Power and Highly Scaled DCT Architecture with CORDIC Algorithm. IJCA Proceedings on National Conference on Power Systems and Industrial Automation NCPSIA 2015(1):12-16, December 2015. Full text available. BibTeX

@article{key:article,
	author = {Bhaskar S.v. and Easwara M.},
	title = {Article: Design and Implementation of Low Power and Highly Scaled DCT Architecture with CORDIC Algorithm},
	journal = {IJCA Proceedings on National Conference on Power Systems and Industrial Automation},
	year = {2015},
	volume = {NCPSIA 2015},
	number = {1},
	pages = {12-16},
	month = {December},
	note = {Full text available}
}

Abstract

This project deals with the hardware implementation of the DCT and IDCT algorithm in a more efficient way by the use of CORDIC algorithm. DCT and IDCT are the most widely used transform technique in Digital Image Processing and Digital Signal Processing. This project presents an efficient approach for multiplier less implementation for N-point DCT approximation, which based on coordinate rotation digital computer (CORDIC) algorithm which makes use of shift and add operation for computation. The proposed algorithm is the most popular because of its computational efficiency and structural simplicity. It has advantages such as regular data flow, uniform post scaling factor, arithmetic sequence rotation angels. In this project an N- point DCT is deduced using two N/2-point DCTs by using orthogonal properties of DCT and IDCT,and also adders are replaced by carry skip adder [1]. Signal flow of 8-point DCT and IDCT CORDIC algorithm are coded and functionality of the design will check using ModelSim simulator. The design will synthesize using Cadence and Xilinx ISE Synthesis tool and the bit file will dumped to a Spartan 3 FPGA kit.

References

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