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Design and Power Analysis of Memory System using Conventional 6T, Sleepy Stack 8T and Single Ended 6T SRAM cell

Published on December 2015 by Thanuja T.c., Kavya M.p.
National Conference on Power Systems and Industrial Automation
Foundation of Computer Science USA
NCPSIA2015 - Number 3
December 2015
Authors: Thanuja T.c., Kavya M.p.
2d02d8b6-61a6-43f9-b4a0-8d00b77843d8

Thanuja T.c., Kavya M.p. . Design and Power Analysis of Memory System using Conventional 6T, Sleepy Stack 8T and Single Ended 6T SRAM cell. National Conference on Power Systems and Industrial Automation. NCPSIA2015, 3 (December 2015), 10-14.

@article{
author = { Thanuja T.c., Kavya M.p. },
title = { Design and Power Analysis of Memory System using Conventional 6T, Sleepy Stack 8T and Single Ended 6T SRAM cell },
journal = { National Conference on Power Systems and Industrial Automation },
issue_date = { December 2015 },
volume = { NCPSIA2015 },
number = { 3 },
month = { December },
year = { 2015 },
issn = 0975-8887,
pages = { 10-14 },
numpages = 5,
url = { /proceedings/ncpsia2015/number3/23341-7260/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on Power Systems and Industrial Automation
%A Thanuja T.c.
%A Kavya M.p.
%T Design and Power Analysis of Memory System using Conventional 6T, Sleepy Stack 8T and Single Ended 6T SRAM cell
%J National Conference on Power Systems and Industrial Automation
%@ 0975-8887
%V NCPSIA2015
%N 3
%P 10-14
%D 2015
%I International Journal of Computer Applications
Abstract

Low power design has become the major challenge of present chip designs as leakage power has been rising with scaling of technologies. As the demand for low power and low cost increases, it is very important to design low power, high performance, and fast responding SRAM (Static Random Access Memory) since they are critical component in high performance processors. The Conventional 6T SRAM cell is very much prone to noise during read operation[2]. To overcome the problems in 6T SRAM cell, researchers have proposed different SRAM topologies such as 8T, 9T, 10T etc. bit cell design. These designs can improve the cell stability but suffer from bit line leakage noise. Dynamic power was previously the single largest concern for low-power chip designers, but as the feature size shrinks, the leakage power reduction has become the great challenge for current and future technologies. In this paper, different SRAM cells are used for the power analysis and also single ended 6T SRAM is introduced which reduces the power and area considerably.

References
  1. Nahid Rahman,B. P. Singh "Design of low power SRAM Memory Using 8T SRAM Cell"-IJRTE.
  2. Bhavya Daya, Shu Jiang,Piotr Nowak, Jaffer Sharief "Synchronous SRAM Design", Electrical Engineering Department, University Of Florida.
  3. "CMOS VLSI DESIGN" by Neil Weiste. "CMOS Digital Integrated Circuits" by Sung-Mo Kang and Yusuf Leblebici.
Index Terms

Computer Science
Information Sciences

Keywords

Sram Cell Pre-charge Circuit Sense Amplifier Single Ended Sram Cell .