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Analysis of Various Full-Adder Circuits in Cadence

Published on December 2015 by Manjunath K.m, Abdul Lateef Haroon P.s., Amarappa Pagi, Ulaganathan J.
National Conference on Power Systems and Industrial Automation
Foundation of Computer Science USA
NCPSIA2015 - Number 3
December 2015
Authors: Manjunath K.m, Abdul Lateef Haroon P.s., Amarappa Pagi, Ulaganathan J.
ecc1a08d-3517-4adf-b173-7f8d0e0ef9df

Manjunath K.m, Abdul Lateef Haroon P.s., Amarappa Pagi, Ulaganathan J. . Analysis of Various Full-Adder Circuits in Cadence. National Conference on Power Systems and Industrial Automation. NCPSIA2015, 3 (December 2015), 30-37.

@article{
author = { Manjunath K.m, Abdul Lateef Haroon P.s., Amarappa Pagi, Ulaganathan J. },
title = { Analysis of Various Full-Adder Circuits in Cadence },
journal = { National Conference on Power Systems and Industrial Automation },
issue_date = { December 2015 },
volume = { NCPSIA2015 },
number = { 3 },
month = { December },
year = { 2015 },
issn = 0975-8887,
pages = { 30-37 },
numpages = 8,
url = { /proceedings/ncpsia2015/number3/23345-7269/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on Power Systems and Industrial Automation
%A Manjunath K.m
%A Abdul Lateef Haroon P.s.
%A Amarappa Pagi
%A Ulaganathan J.
%T Analysis of Various Full-Adder Circuits in Cadence
%J National Conference on Power Systems and Industrial Automation
%@ 0975-8887
%V NCPSIA2015
%N 3
%P 30-37
%D 2015
%I International Journal of Computer Applications
Abstract

The Adder is the important part in any processor/controller design. Till date there are a plenty of 1-bit full-adder circuits which have been proposed and designed. In this paper we have a analytic and comparative description of various full adder circuits, considering various constraints like power consumption, speed of operation and area. The circuits are designed in the virtuoso platform, using cadence tool with the available GPDK – 45nm kit. The Full-adder circuits with the most 28 transistor to the one with only 6 transistors are successfully designed, simulated and compared for various parameters like power consumption, speed of operation(delay) and area (transistor count), and finally concluded the best designs, that suite for the particular specifications.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Cadence Virtuoso Gpdk Delay Power Consumption Area (transistor Count)