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Phase Noise Reduction Approach in PLL based Frequency Synthesizer for IEEE1394 PHY Applications

IJCA Proceedings on National Conference on “Recent Trends in Information Technology"
© 2016 by IJCA Journal
NCRTIT 2016 - Number 1
Year of Publication: 2016
Channayya C. H.
Lakshmisha S. Krishna
Ramachandra A. C.

Channayya C H., Lakshmisha S Krishna and Ramachandra A C.. Article: Phase Noise Reduction Approach in PLL based Frequency Synthesizer for IEEE1394 PHY Applications. IJCA Proceedings on National Conference on Recent Trends in Information Technology" NCRTIT 2016(1):27-32, August 2016. Full text available. BibTeX

	author = {Channayya C. H. and Lakshmisha S. Krishna and Ramachandra A. C.},
	title = {Article: Phase Noise Reduction Approach in PLL based Frequency Synthesizer for IEEE1394 PHY Applications},
	journal = {IJCA Proceedings on National Conference on Recent Trends in Information Technology"},
	year = {2016},
	volume = {NCRTIT 2016},
	number = {1},
	pages = {27-32},
	month = {August},
	note = {Full text available}


Technology advances have made gigabit signal a viable and attractive. A method to design IEEE 1394 based 1GHz Phase Locked Loop (PLL) system as frequency synthesizer with Low Phase Noise is proposed. A complementary LC oscillator is used to generate the 1GHz oscillation frequency and is divided into lower frequency clock by the feedback frequency divider. The architecture is type II third order charge pump Phase Locked Loop. In order to suppress spurs and reduce ripples on control voltage a third order loop filter is used. Power consumption is significantly reduced by simplifying the circuit structure of digital frequency divider. Advance process of silicon-Germanium BiCMOS (SiGe) is used to integrate high-performance Hetero-junction Bipolar Transistors (HBTs) and MOSFETs actives and passives. This technology has the advantage that its flicker noise (1/f) is very low.


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