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Phase Noise Reduction Approach in PLL based Frequency Synthesizer for IEEE1394 PHY Applications

Published on August 2016 by Channayya C. H., Lakshmisha S. Krishna, Ramachandra A. C.
National Conference on “Recent Trends in Information Technology"
Foundation of Computer Science USA
NCRTIT2016 - Number 1
August 2016
Authors: Channayya C. H., Lakshmisha S. Krishna, Ramachandra A. C.
68d35100-e33e-45ba-bb53-348fb18adaaa

Channayya C. H., Lakshmisha S. Krishna, Ramachandra A. C. . Phase Noise Reduction Approach in PLL based Frequency Synthesizer for IEEE1394 PHY Applications. National Conference on “Recent Trends in Information Technology". NCRTIT2016, 1 (August 2016), 27-32.

@article{
author = { Channayya C. H., Lakshmisha S. Krishna, Ramachandra A. C. },
title = { Phase Noise Reduction Approach in PLL based Frequency Synthesizer for IEEE1394 PHY Applications },
journal = { National Conference on “Recent Trends in Information Technology" },
issue_date = { August 2016 },
volume = { NCRTIT2016 },
number = { 1 },
month = { August },
year = { 2016 },
issn = 0975-8887,
pages = { 27-32 },
numpages = 6,
url = { /proceedings/ncrtit2016/number1/25583-1623/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on “Recent Trends in Information Technology"
%A Channayya C. H.
%A Lakshmisha S. Krishna
%A Ramachandra A. C.
%T Phase Noise Reduction Approach in PLL based Frequency Synthesizer for IEEE1394 PHY Applications
%J National Conference on “Recent Trends in Information Technology"
%@ 0975-8887
%V NCRTIT2016
%N 1
%P 27-32
%D 2016
%I International Journal of Computer Applications
Abstract

Technology advances have made gigabit signal a viable and attractive. A method to design IEEE 1394 based 1GHz Phase Locked Loop (PLL) system as frequency synthesizer with Low Phase Noise is proposed. A complementary LC oscillator is used to generate the 1GHz oscillation frequency and is divided into lower frequency clock by the feedback frequency divider. The architecture is type II third order charge pump Phase Locked Loop. In order to suppress spurs and reduce ripples on control voltage a third order loop filter is used. Power consumption is significantly reduced by simplifying the circuit structure of digital frequency divider. Advance process of silicon-Germanium BiCMOS (SiGe) is used to integrate high-performance Hetero-junction Bipolar Transistors (HBTs) and MOSFETs actives and passives. This technology has the advantage that its flicker noise (1/f) is very low.

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Index Terms

Computer Science
Information Sciences

Keywords

Phase Locked Loop Mixed Signal Simulation Vco Frequency Divider Passive Filter Sige.