Flip-Flops are off many types. Choosing the correct type FF for any application is very important to achieve high performance. the data look ahead d Flip-Flop (DLDFF) from the family of master-slave type is compared with pulse triggered conditional capture Flip-Flop(CCFF). The effect of clock gating on the performance of these Flip-Flops are analyzed. The two Flip-Flops are compared, with clock gating for power and delay and their field of application is determined. Our simulation results in 0. 18µm CMOS technology in HSPICE indicates that DLDFF, for various load values 75% power and 60% delay reduction than DFF due to gating. but Clock Gated CCFF consumes more power on increasing load. Hence for applications that include large load, DLDFF will be the best choice. CGCCFF works well on high frequencies applications with 75% power reduction and 60% higher performance than CCFF. A 8-bit synchronous counter is implemented DLDFF and CGCCFF saves 38% and 15% power consumption on clock gating than DFF and CCFF counterparts. The Pavg obtained for CGCCFF is proved as very much high when compared to DLDFF due to the increased load in couter. Hence it is determined that DLDFF is works well on large circuits and CGCCFF for high frequency applications.

1. V. Stojanovicetal. , "Comparative analysis of master–slave latches and fl ip–fl ops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, pp. 536–548, April. 1999.
2. M. Nogawa and Y. Ohtomo, "A Data-Transition Look-Ahead DFF circuit for Statistical Reduction in power consumption," IEEE J. Solid State Circuits, Vol. 33, pp. 702–706, May, 1998.
3. H. Jacobson, P. Bose, Z. Hu, A. Buyuktosunoglu, V. Zyuban, R. Eickemeyer, L. Eisen, J. Griswell, D. Logan, B. Sinharoy, and J. Tendler, "Stretching the limits of clock-gating efficiency in server lass processors," in Proc. Int. Symp. High-Perform Compute. Archit. , pp. 238–242, Feb. 2005.
4. S. Vinoth Kumar and M. Malathi, "Low Power Condi-tional Capture Flip-Flop with Clock Gating" Proceedings of the International Conference on VLSI, Communication and Instrumentation [ICVCI-2011] pp. 443-446, Apr, 7th – 9th, 2011, SAINTGITS College of Engg, Kottayam, INDIA.
5. B. S. Kong etal. "Conditional- Capture Flip-Flop Technique for Statistical Power Reduction, "in Int. Solid-State Circuits Conf. , Dig. of Tech. Papers, pp. 290–291, February, 2000.
6. Young-Won Kim, Joo-Seong Kim, Jae-Hyuk Oh, Yoon-Suk Park, Jong-Woo Kim, Kwang-Il Park, Bai-Sun Kong, and Young-Hyun Jun, "Low – Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation," IEEE Transactions on Circuits And Systems— Ii: Express briefs, Vol. 56, No. 8, pp. 649-653, August 2009.
7. M. R. Stan, A. F. Tenca , and M. D. Ercegovac , "Long and fast up/down Counter ," IEEE Trans . Comput. ,vol. 47,no. 7,pp. 722– 735, Jul. 1998.
8. Jan M. Rabaey, Digital Integrated Circuits, PHI LEARNING Private Limited. Edition – 2003.
9. N. H . E . Weste and D . Harris, CMOS VLSI Design. Reading, MA: Pearson Education, Inc. , 2005.
10. H. Jacobson, P. Bose, Z. Hu, A. Buyuktosunoglu, V. Zyuban, R. Eickemeyer, L. Eisen, J. Griswell, D. Logan, B. Sinharoy, and J. Tendler, "Stretching the limits of clock-gating efficiency in server lass processors," in Proc. Int. Symp. High-Perform Compute. Archit. , pp. 238–242, Feb. 2005.
11. S. H. Unger et al. , "Clocking schemes for high-speed digital systems," IEEE Trans. Comput. , vol. C-35, pp. 880–895, October 1986.
12. H. Partovietal. , "Flow-through latch and edge-triggered flip-fl op hybrid elements," in Int . Solid-State Circuits Conf. Dig. of Tech. Papers, pp. 138–139, February1996

Clock Gating Data Look Ahead Conditional Capture Young's Architecture Low Power