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Reseach Article

Implementation of a High Speed Single Precision Floating Point Unit using Verilog

Published on March 2013 by Ushasree G, R Dhanabal, Sarat Kumar Sahoo and
National Conference on VLSI and Embedded Systems
Foundation of Computer Science USA
NCVES - Number 1
March 2013
Authors: Ushasree G, R Dhanabal, Sarat Kumar Sahoo and
1275996b-728b-4c61-a9ce-9a562792aab1

Ushasree G, R Dhanabal, Sarat Kumar Sahoo and . Implementation of a High Speed Single Precision Floating Point Unit using Verilog. National Conference on VLSI and Embedded Systems. NCVES, 1 (March 2013), 32-36.

@article{
author = { Ushasree G, R Dhanabal, Sarat Kumar Sahoo and },
title = { Implementation of a High Speed Single Precision Floating Point Unit using Verilog },
journal = { National Conference on VLSI and Embedded Systems },
issue_date = { March 2013 },
volume = { NCVES },
number = { 1 },
month = { March },
year = { 2013 },
issn = 0975-8887,
pages = { 32-36 },
numpages = 5,
url = { /proceedings/ncves/number1/11311-1308/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Conference on VLSI and Embedded Systems
%A Ushasree G
%A R Dhanabal
%A Sarat Kumar Sahoo and
%T Implementation of a High Speed Single Precision Floating Point Unit using Verilog
%J National Conference on VLSI and Embedded Systems
%@ 0975-8887
%V NCVES
%N 1
%P 32-36
%D 2013
%I International Journal of Computer Applications
Abstract

To represent very large or small values, large range is required as the integer representation is no longer appropriate. These values can be represented using the IEEE-754 standard based floating point representation. This paper presents high speed ASIC implementation of a floating point arithmetic unit which can perform addition, subtraction, multiplication, division functions on 32-bit operands that use the IEEE 754-2008 standard. Pre-normalization unit and post normalization units are also discussed along with exceptional handling. All the functions are built by feasible efficient algorithms with several changes incorporated that can improve overall latency, and if pipelined then higher throughput. The algorithms are modeled in Verilog HDL and have been implemented in ModelSim.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Floating Point Number Normalization Exceptions Latency