CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
Reseach Article

Partitioning VLSI Circuits

Published on May 2012 by Geetika, Amardeep Singh
National Workshop-Cum-Conference on Recent Trends in Mathematics and Computing 2011
Foundation of Computer Science USA
RTMC - Number 15
May 2012
Authors: Geetika, Amardeep Singh
d482579d-4e34-4a31-90cd-93831ed8163f

Geetika, Amardeep Singh . Partitioning VLSI Circuits. National Workshop-Cum-Conference on Recent Trends in Mathematics and Computing 2011. RTMC, 15 (May 2012), 26-28.

@article{
author = { Geetika, Amardeep Singh },
title = { Partitioning VLSI Circuits },
journal = { National Workshop-Cum-Conference on Recent Trends in Mathematics and Computing 2011 },
issue_date = { May 2012 },
volume = { RTMC },
number = { 15 },
month = { May },
year = { 2012 },
issn = 0975-8887,
pages = { 26-28 },
numpages = 3,
url = { /proceedings/rtmc/number15/7147-1122/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 National Workshop-Cum-Conference on Recent Trends in Mathematics and Computing 2011
%A Geetika
%A Amardeep Singh
%T Partitioning VLSI Circuits
%J National Workshop-Cum-Conference on Recent Trends in Mathematics and Computing 2011
%@ 0975-8887
%V RTMC
%N 15
%P 26-28
%D 2012
%I International Journal of Computer Applications
Abstract

Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits it is often essential to sub-divide a circuit into smaller parts. Circuit partitioning plays an important role in physical design automation of very large scale integration (VLSI) chips. In VLSI circuit partitioning the problem of obtaining minimum cut is of prime importance. To enhance other criteria like power, delay and area in addition to minimum cit is included.

References
  1. FrankM. Johannes Institute of Electronic Design Automation ECE Department, Technical University of Munich Arcisstr. 21, D-80333 Munich, Germany E-mail: Johannes@e-technik. tu-muenchen. de
  2. Johannes, F. M," Partitioning of VLSI circuits and systems", This paper appears in Design Automation Conference Proceedings 1996,33rd Publication Date: 3-7 Jun, 1996 On page(s): 83-87
  3. B. W. Kernighan and S. Lin, An Efficient Heuristic Procedure for Partitioning Graphs", Bell System Tech. Journal volume. 49,Feb. 1970, pp. 291-307.
  4. C. M. Fiduccia and R. M. Mattheyses, "A Linear-time heuristic for Improving Network partitions" Proc. ACM/IEEE Design Automation Conf. , 1982, pp 175-181
  5. Augeri,C. J. ;Ali,H. H "New Graph Based Algorithms For Partitioning VLSI Circuits"Circuits aSystems ,2004. ISCAS apos ;04. Proceeding of the 2004 International Symposium on Volume 3,Issue , 23-26 May 2004
  6. . Raslam Hasim Al Abaji Evolutinary techniques for partitioning VlSI circuits. Department of computer engineering May 2001.
  7. . K. A Sumitra Devi ,N. P Banashree and Annamma Abraham. Comparitive study of Evolutionary Model and Clustering Methods in VLSI circuit Partitioning.
Index Terms

Computer Science
Information Sciences

Keywords

Vlsi Circuit Partitioning delay cut Size