CFP last date
20 March 2024
Reseach Article

Analyzing Methodologies of Irregular NoC Topology Synthesis

Published on December 2011 by Naveen Choudhary, Dharm Singh, Surbhi Jain
Communication and Networks
Foundation of Computer Science USA
COMNETCN - Number 1
December 2011
Authors: Naveen Choudhary, Dharm Singh, Surbhi Jain

Naveen Choudhary, Dharm Singh, Surbhi Jain . Analyzing Methodologies of Irregular NoC Topology Synthesis. Communication and Networks. COMNETCN, 1 (December 2011), 35-39.

author = { Naveen Choudhary, Dharm Singh, Surbhi Jain },
title = { Analyzing Methodologies of Irregular NoC Topology Synthesis },
journal = { Communication and Networks },
issue_date = { December 2011 },
volume = { COMNETCN },
number = { 1 },
month = { December },
year = { 2011 },
issn = 0975-8887,
pages = { 35-39 },
numpages = 5,
url = { /specialissues/comnetcn/number1/5446-1009/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Special Issue Article
%1 Communication and Networks
%A Naveen Choudhary
%A Dharm Singh
%A Surbhi Jain
%T Analyzing Methodologies of Irregular NoC Topology Synthesis
%J Communication and Networks
%@ 0975-8887
%N 1
%P 35-39
%D 2011
%I International Journal of Computer Applications

Network-On-Chip (NoC) provides a structured way of realizing communication for System on Chip (SoC) with many processing cores, which emphasize a communication-centric, as opposed to a computation-centric, design view. Network-on-Chip architectures have a wide variety of parameters that can be optimized according to the designer’s requirements. Exploration and optimization of these parameters is an active area of research and a large number of methodologies have been proposed for this. In this paper we study the existing techniques and categorize them on the basis of considered optimization objectives.

  1. Dally, W. J., and Towles, B. 2001. Route Packet Not Wires: On-Chip Interconnection Networks. In IEEE Proceedings of the 38th Design Automation Conference (DAC), pp. 684–689.
  2. Bjerregaard, T., and Mahadevan, S. 2006. A Survey of Research and Practices of Network-on-Chip. In ACM Computing Surveys, Vol. 38, March 2006, Article 1.
  3. Duato, J., Yalamanchili, S., and Ni, L. 2003. Interconnection Networks: An Engineering Approach, Elsevier.
  4. International technology roadmap for semiconductors. Semiconductor Industry Association, 2003
  5. Choudhary, N., Gaur, M. S., and Laxmi, V. 2011. Irregular NoC Simulation Framework: IrNIRGAM. In IEEE International conference on Emerging Trends in Network and Computer Communications (ETNCC), Udaipur, India.
  6. Benini, L. 2006 Application Specific NoC Design. DEIS Universit´a di Bologna, IEEE website.
  7. Srinivasan, K., Chatha, K. S. 2005. Isis: a genetic algorithm based technique for custom on-chip interconnection network synthesis. 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design. Kolkata, India, pp: 623-628.
  8. Srinivasan, K., and Chatha, K. S. 2005. SAGA: Synthesis Technique for Guaranteed Throughput NoC Architectures. ASP-DAC 2005.
  9. Srinivasan, K., Chatha, K. S., and Konjevod, G, 2004. Linear Programming Based Techniques for Synthesis of Network-on-Chip Architectures. In Proceedings of ICCD.
  10. Gu, H., Xu, J., and Zhang, W. 2009. A Low-Power Fat Tree-based Optical Network-on-Chip for Multiprocessor System-on-Chip. In Design, Automation & Test in Europe Conference & Exhibition, 2009.
  11. Choudhary, N., Gaur, M.S., Laxmi, V., and Singh, V. 2011. GA Based Congestion Aware Topology Generation for Application Specific NoC. in: Electronic Design, Test and Application (DELTA), 2011 Sixth IEEE International Symposium.
  12. Choudhary, N., Gaur, M.S., Laxmi, V., and Singh, V. 2010. Energy aware design methodologies for application specific NoC. In NORCHIP, 2010.
  13. Jain, L., Al-Hashimi, B.M., Gaur, M.S, Laxmi, V. and Narayanan, A. 2007. NIRGAM: A Simulator for NoC Interconnect Routing and Application Modelling. Proc. DATE 2007.
  14. Hu, J., and Marculescu, R. 2003. Energy-aware mapping for tile-based NoC architectures under performance constraints. ASP-DAC 2003.
  15. Wang, J., Li, Y., Chai, S., and Peng, Q. 2011. Bandwidth-Aware Application Mapping for NoC-Based MPSoCs. In Journal of Computational Information Systems 7:1 (2011) 152-159.
  16. Fekr, A. R., Khademzadeh, A., Janidarmian, M., and Bokharaei, V. S. 2010. Bandwidth/Fault tolerance/ Contention Aware Application-Specific NoC Using PSO as a Mapping Generator. Proceedings of the World Congress on Engineering 2010 Vol I.
  17. Qi, J., Zhao, H., Wang,J., and Li, Z. 2010. A new hierarchical genetic algorithm for low-power network on chip design. In Intelligent Control and Information Processing (ICICIP), 2010 International Conference.
  18. Ascia, G., Catania, V., and Palesi, M. 2006. A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. In Journal of Universal Computer Science, vol. 12, no. 4, 370-394.
Index Terms

Computer Science
Information Sciences


Network-on-Chip (NoC) NoC communication graph Genetic algorithm Particle swarm optimization Ant colony optimization