Notification: Our email services are now fully restored after a brief, temporary outage caused by a denial-of-service (DoS) attack. If you sent an email on Dec 6 and haven't received a response, please resend your email.
CFP last date
20 December 2024
Reseach Article

Impact of Width Variation of Global Inductive VLSI Interconnect Line

Published on December 2011 by Diwakar Singh, Gargi Khanna, Rajeevan Chandel
International Conference on Electronics, Information and Communication Engineering
Foundation of Computer Science USA
ICEICE - Number 6
December 2011
Authors: Diwakar Singh, Gargi Khanna, Rajeevan Chandel
0cbf4c5c-22d4-47f5-bfc3-444afb2d79b0

Diwakar Singh, Gargi Khanna, Rajeevan Chandel . Impact of Width Variation of Global Inductive VLSI Interconnect Line. International Conference on Electronics, Information and Communication Engineering. ICEICE, 6 (December 2011), 1-4.

@article{
author = { Diwakar Singh, Gargi Khanna, Rajeevan Chandel },
title = { Impact of Width Variation of Global Inductive VLSI Interconnect Line },
journal = { International Conference on Electronics, Information and Communication Engineering },
issue_date = { December 2011 },
volume = { ICEICE },
number = { 6 },
month = { December },
year = { 2011 },
issn = 0975-8887,
pages = { 1-4 },
numpages = 4,
url = { /specialissues/iceice/number6/4309-iceice042/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 International Conference on Electronics, Information and Communication Engineering
%A Diwakar Singh
%A Gargi Khanna
%A Rajeevan Chandel
%T Impact of Width Variation of Global Inductive VLSI Interconnect Line
%J International Conference on Electronics, Information and Communication Engineering
%@ 0975-8887
%V ICEICE
%N 6
%P 1-4
%D 2011
%I International Journal of Computer Applications
Abstract

In this paper the impact of width variation is being addressed on transition time, power dissipation and crosstalk noise in coupled inductive lines for different switching patterns. The finding of simulation reveals that there is first decrease in transition delay and then it increases afterwards. It is also observed that power increases slowly with width increasing and also observed the crosstalk noise at the victim line for the increase in width.

References
  1. International Technology Roadmap for Semiconductors, Available: http://public.itrs.net
  2. A. Naeemi, R. Venkatesan, and J. D. Meindl, “System-On-a-Chip global interconnect optimization”, Proc. IEEE on ASIC/SOC Conference, pp. 399-403, Sep. 2002.
  3. X. C. Li, J. F. Mao, H. F. Huang, and Y. Liu, “Global interconnect width and spacing optimization for latency, bandwidth and power dissipation”, IEEE Trans. Elec. Dev., pp. 2272-2279, Oct. 2005.
  4. Y. I. Ismail and E. G. Friedman, “Effects of inductance on the propagation delay and repeater insertion in VLSI circuits”, IEEE Trans. on VLSI Systems, vol. 8, pp. 195-206, Apr. 2000.
  5. Xuejue Huang, et al., “RLC signal integrity analysis of high speed global interconnects”, IEDM Technical Digest International Electron Devices, pp. 731-734, Dec. 2004.
  6. Shang-Wei Tu, Yao-Wen Chang, and Jing-Yang Jou, “RLC coupling aware simulation and on-chip bus encoding for delay reduction”, IEEE Trans. of Computer Aided Design, vol. 25, no. 10, pp. 2258-2264, Oct. 2006.
  7. R. Venkatesan, J. A. Davis, and J. D. Meindl, “Compact distributed RLC interconnect models-Part III: Transients in single and coupled lines with capacitive load termination," IEEE Trans. Electron Devices, Vol. 50, pp.1081-1093, Apr. 2003.
  8. R. Venkatesan, J. A. Davis, and J. D. Meindl, “Compact Distributed RLC Interconnect Models-Part IV: Unified Models for Time Delay, Crosstalk, and Repeater Insertion”, IEEE Trains. Electron Devices, vol. 50. pp.1094-1102, Apr. 2003.
  9. Abinash Roy, Noha Mahmoud and M. H. Chowdhury, “Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew”, Design Automation Conference, pp. 184-187, Jun. 2007.
  10. M.A. El-Moursy, E.G. Friedman, “Inductive interconnect width optimization for low power" Proc. IEEE Symp. Circuits and Systems, pp. 5.273-5.276, May 2003.
  11. K. Banerjee and A. Mehrotra, “Accurate analysis of on-chip effects using a novel performance optimization methodology for distributed RLC ipterconnnects,” in Proc. Design Automation Conf, Las Vegas, NV, pp. 798-803, 2001.
  12. K. Banerjee and A. Mehrotra, “Analysis of on-chip inductance effects for distributed RLC interconnects,” IEEE Trans. Computer-Aided Design, vol. 21, pp. 904-915, Aug. 2002.
  13. Y. 1. Ismail and E. G. Friedman, “Effects of inductance on the propagation delay and repeater insertion in VLSI circuits,” IEEE Trans. VLSI Syst., vol. 8, pp. 195-206, Apr. 2000.
  14. Y. 1. Ismail, E. G. Friedman, and J. L. Neves, “Figures of merit to characterize the importance of on-chip inductance,” IEEE Tratns. VLSI Svs.. Vol. 7, pp.442-449, Dec 1999.
  15. Y.I.Ismail, E.G.Friedman, and J.L.Neves, “Exploiting the on-chip Inductance in High-speed clock distribution networks,” IEEE Trans. VLSI Syst., vol. 9, Dec. 2001.
  16. A. B. Kahng and S. Muddu, “An analytical delay model for RLC interconnects,” IEEE Trtns. Computer-Aided Design, vol. 16, pp. 1507-1514, Dec. 1997.
Index Terms

Computer Science
Information Sciences

Keywords

Power Dissipation Inductive VLSI Interconnect Line Signal Skew