Call for Paper - July 2022 Edition
IJCA solicits original research papers for the July 2022 Edition. Last date of manuscript submission is June 20, 2022. Read More

Performance Evaluation of Traffic Permutations for Mesh On-Chip Networks

Print
PDF
IJCA Special Issue on Optimization and On-chip Communication
© 2012 by IJCA Journal
ooc - Number 1
Year of Publication: 2012
Authors:
Naveen Choudhary
Dharm Singh
Abhilasha Sharma

Naveen Choudhary, Dharm Singh and Abhilasha Sharma. Article: Performance Evaluation of Traffic Permutations for Mesh On-Chip Networks. IJCA Special Issue on Optimization and On-chip Communication ooc(1):6-10, February 2012. Full text available. BibTeX

@article{key:article,
	author = {Naveen Choudhary and Dharm Singh and Abhilasha Sharma},
	title = {Article: Performance Evaluation of Traffic Permutations for Mesh On-Chip Networks},
	journal = {IJCA Special Issue on Optimization and On-chip Communication},
	year = {2012},
	volume = {ooc},
	number = {1},
	pages = {6-10},
	month = {February},
	note = {Full text available}
}

Abstract

Networks-on-Chip (NoC) is recently proposed as an alternative to the on-chip bus to meet the increasing requirement of complex communication needs in Systems-on-Chip (SoC). Using on-chip interconnection networks in place of ad-hoc global wiring, structures the top level wires on a chip and facilitates modular design. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. Using a network to replace global wiring has advantages of structure, performance, and modularity. With this approach, system modules (processors, memories, peripherals, etc.) communicate by sending packets to one another over the network. In NoC, nodes are arranged in the topology such that communication between any nodes is possible even though they are not directly connected. Each node is a IP core which can be a DSP, Microprocessor, Memory along with routing function which is responsible for forwarding the data packet to the neighboring node.

References

  • Dally, W.J., Towles, B. 2001 Route Packets, Not Wires: On-Chip Interconnection Networks. In IEEE Proceedings of the 38th Design Automation Conference (DAC), 684–689
  • Benini, L., DeMicheli, G. 2002 Networks on Chips: A New SoC Paradigm. In IEEE Computer Vol. 35, No. 1, 70–78
  • Choudhary, N., Gaur, M.S., Laxmi, V. Irregular NoC Simulation Framework :IrNIRGAM
  • Du, G., Zhang, D., Song, Y., Gao, M., Geng, L. 2008 Scalability Study on Mesh based Network on chip. In IEEE Pacific-Asia Workshop on Computational Intelligence and Industrial Application
  • J. Duato, S. Yalamanchili, L. Ni, Interconnection Networks: An Engineering Approach, Elsevier, 2003
  • Bjerregaard, T., Mahadevan, S. 2006 A Survey of research and practices of network-on-chip. In Acm computing Surveys, vol.38, No.11-51.
  • Jain, Lavina, Al-Hashimi, B.M, Gaur, M.S, Laxmi V and Narayanan, A, “NIRGAM: A Simulator for NoC Interconnect Routing and Application Modelling, Proc. DATE 2007, 2007
  • Brown, L. D., Hua, H., and Gao, C. 2003. A widget framework for augmented interaction in SCAPE.