The week's pick
Random Articles
Reseach Article
A Modern Parallel Register Sharing Architecture for Code Compilation
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 1 - Number 16 |
| Year of Publication: 2010 |
| Authors: Rajendra Kumar, P. K. Singh |
10.5120/334-505
|
Rajendra Kumar, P. K. Singh . A Modern Parallel Register Sharing Architecture for Code Compilation. International Journal of Computer Applications. 1, 16 ( February 2010), 95-99. DOI=10.5120/334-505
Abstract
The design of many-core-on-a-chip has allowed renewed an intense interest in parallel computing. On implementation part, it has been seen that most of applications are not able to use enough parallelism in parallel register sharing architecture. The exploitation of potential performance of superscalar processors has shown that processor is fed with sufficient instruction bandwidth. The fetcher and the Instruction Stream Buffer (ISB) are the key elements to achieve this target. Beyond the basic blocks, the instruction stream is not supported by currents ISBs. The split line instruction problem depreciates this situation for x86 processors. With the implementation of Line Weighted Branch Target Buffer (LWBTB), the advance branch information and reassembling of cache lines can be predicted by the ISB. The ISB can fetch some more valid instructions in a cycle through reassembling of original line containing instructions for next basic block. If the cache line size is more than 64 bytes, then there exist good chances to have two basic blocks in the recognized instruction line.
References
- Aho, A. V., R. Sethi, and J. D. Ullman, “Compilers. Principles, Techniques and Tools”, Addison Wesley, 2000.
- Alex G., Avi M. Assaf S., Gregory S., Code Compilation for an Explicitly Parallel Register-Sharing Architecture, IEEE International Conference on Parallel Processing, 2007
- C. Lee, M. Potkonjak, W. H. Mangoine-Smith, “Mediabench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems”, 30th Annual ACM International Symposium on Microarchitecture, 1997
- D. Burger, T. M. Tustin, S. Bennet, “Evaluating Future Microprocessors: The SimpleScalar Tool Set”, Technical Report CS-TR, University of Wisconsin Madison, 1996
- D. Grunwald, H. Srinivasan, “Data Flow Equations for Explicitly Parallel Programs”, Fourth ACM SIGPLAN symposium on Principles and Practice of Parallel Programming, 1993
- D. M. Tullsen, S. Eggers, H. M. Levy, “Simultaneous Multithreading: Maximizing on-chip Parallelism”, Proceeding of the 22th Annual International Symposium on Computer Architecture, 1995
- David I. August Wen-mei W. Hwu Scott A. Mahlke, The Partial Reverse If-Conversion Framework for Balancing Control Flow and Predication, International Journal of Parallel Programming Volume 27, Issue 5, Pages: 381 – 423, 1999
- Dionisios N. Pnevmatikatos Manoj Franklin, Control Flow Prediction for Dynamic ILP Processors, Proceedings of the 26th Annual International Symposium on Micro-architecture, 1993
- Guilin Chen, Mahmut Kandemir, Compiler-Directed Code Restructuring for Improving Performance of MPSoCs, IEEE Transactions on Parallel and Distributed Systems, Vol. 19, No. 9, 2008
- J. Cong, Guoling Han, Zhiru Zhang, “Architecture and compilation for data bandwidth improvement in configurable embedded processors”, IEEE International Conference on Computer Aided Design, Proceedings of the 2005
- J. L. Henning, “SPEC CPU 2000: Measuring CPU Performance in the new Millennium”, Computer 33(7), 2000
- L. Hammond, B. A. Nayfeh, K. Olukotun, “A single chip Multiprocessor”, IEEE Computer Special Issue on Billion-Transistor Processor, 30(9), 1997
- Marcos, Keali, “Exposing instruction level parallelism in the presence of loops”, Computation Systems Vol. 8 Number 1, pp. 074-085, 2004
- Noah Snavely, Saumya Debray, Gregory R. Andrews, Unpredication, Unscheduling, Unspeculation: Reverse Engineering Itanium Executable, IEEE Transactions on Software Engineering, Volume 31 Issue 2, 2005
- S. Muchnik, “Advanced compiler design and implementation”, Morgan Kaufmann Publishing, 1997
- Shaoshan Liu Gaudiot, J. L., The potential of fine-grained value prediction in enhancing the performance of modern parallel machines, Computer Systems Architecture Conference, 2008
- Steve Car, Combining Optimization for Cache and Instruction-Level Parallelism, Proceedings of PACT’96, 1996
- Siwei Shen, David Flanagan, Siu-Chung Cheung, “An Extended Heuristic for Hyper-block Selection in If-Conversion”, Department of Electrical Engineering and Computer Science University of Michigan, Ann Arbor, Michigan 48109, USA
- Su-Hui Chiang and Sangsuree Vasupongayya, Design and Potential Performance of Goal-Oriented Job Scheduling Policies for Parallel Computer Workloads, IEEE Transactions on Parallel and Distributed Systems, Vol. 19, no. 12, December 2008.
- Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, and Sarita Adve, “The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors”, IEEE Transactions on Computers, Volume 48, Issue 2, Special issue on cache memory and related problems, pp 218-226, 1999
Index Terms
Keywords